I thought there is a generic design guide in 7xxx series from IPC,  
but not as compliances.  As for electrical clearance in Z dimension  
of assembly stack, your design call the shot.  it need to be defined  
not only static condition of clearance, but also dynamic condition-  
for example, what happen when the assembly drop on impact, is it  
clearance still maintained or will it be short to the two vertical  
functional layers or mechanically damage the one of the parts.  only  
your designer can answer that (based on the assembly/system  
requirements).
based on early email, look like two supply of the parts, one is OK,  
the other is not... there is a problem  of equivalent but not  
better... sourcing issues... (or loose design control, if it forgot  
to put tolerance on it... or you have a free spirit buyer out  
there... hard to say what is your problem.  don't think ipc is going  
to fix it... training your designer or buyer might be a better  
solution).
my 1.5 cents.
           jk
On Oct 20, 2015, at 11:40 AM, Jack Olson wrote:

> That spec doesn't regulate what a designer chooses to do. It just  
> defines the acceptability of downstream processes like placement,  
> soldering, etc.
> For the record, the designer can break every good guideline if he  
> wants to, as long as he doesn't hold the assembler responsible for  
> the result, thus the need for AABUS (As Agreed Between User and  
> Supplier)
> UNLESS your condition was caused by the assembler placing the caps  
> or connector INCORRECTLY,
> you should maybe get a signed waiver for the design to CYA


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