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September 2015

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Subject:
From:
Jason Zhao <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Jason Zhao <[log in to unmask]>
Date:
Thu, 10 Sep 2015 16:32:41 -0500
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text/plain
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Hi Ravinder,

Here are my answers
1. Yes, top/bottom layers go through the normal plating process that adds
about 1-1.5 mils of copper. 
2. After solder mask, only on the areas not covered by solder mask
3. Solder mask is applied before ENIG
4. 2 mils is about right. 

Best regards,

Jason Zhao
VP of North America Operations
Sunshine Global PCB Group
US Cell 510-468-4412, China Cell 131-62722392
www.sunshinepcbgroup.com
Come see us at the PCB West Exhibition, Booth #208



-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ravinder Ajmani
Sent: Thursday, September 10, 2015 4:11 PM
To: [log in to unmask]
Subject: [TN] Board with Nickel/Gold plating

Hi Experts,

I am designing a high-speed measurement board.  The board will have a dozen
high-speed signals connected to 2.92 mm connectors.  The signal traces will
be routed on the Top layer with through vias at the two ends.  I have been
advised to plate the signal traces with 3 - 10 microinches of Gold over 100
microinches of Nickel.  Solder Mask/Conformal Coat will not be applied over
the signal traces and via pads.  No components need to be soldered to the
signal traces, and 2.92 mm connectors will be screwed to the board.

I am trying to get an understanding of the board fabrication process to
determine the finished thickness of the signal traces.  This will help me
figure out the trace impedance.  I will appreciate if you can provide
answers to the following:


*        The starting Copper thickness for the Top/Bottom layers will be 0.6
mils (1/2 oz).  Will Top/Bottom layers still go through the normal plating
process.

*        At what stage will Nickel and Gold be plated on the board.  Also is
it plated on the entire board surface or only the exposed locations (signal
traces and vias).

*        Is solder mask applied in the final stage (after the ENIG process).

*        What is the expected finished thickness of the signal traces.  I
was informed by the Fab personnel that this will be about 2 mils.

Thank you very much for your help.

Regards

Ravinder Ajmani
HGST, a Western Digital company
[log in to unmask]<mailto:[log in to unmask]>

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