Double the customer's estimate, then change to the next higher unit of
measure, e.g., 5 days becomes 10 days becomes 10 weeks.

On Thu, Sep 10, 2015 at 5:03 PM, Dave <[log in to unmask]> wrote:

> What's with the formatting .....?
>       From: Dave <[log in to unmask]>
>  To: [log in to unmask]
>  Sent: Thursday, September 10, 2015 3:34 PM
>  Subject: Re: [DC] Estimating PCB Design time
>
> Hi Mr. Brooks, I like your questions. I find them entertaining and
> enlightening. A few days ago I sent an email and the formatting was very
> different from what I originally sent and a Venn diagram that I pasted into
> the email got filtered out. Perhaps someone from the IPC server side should
> look into that. (off topic)  That Venn diagram that I originally pasted
> displayed "QUALITY - COST - TIME" each being 1/3 of a circle yet
> overlapping of course. Our clients (most often our managers) want all three
> (Low Cost, Fast Design Cycle, and High Quality) and this Venn diagrammed
> perfectly described this as UNREALISTIC ... So you ask: What get's in the
> way? What slows you down? What makes you work harder?That's obvious ...
> Management is the first answer to all three. They want all four, Done Fast,
> High Quality, and Cheap.I've seen many designs fail and take significantly
> longer because management failed to listen to their Engineers
> predictions. They push, they prod yet they are often out of touch with
> reality. I suggest to all mangers reading this to have some fun and do a
> design yourself once in a while from (front to back). Let's see how you get
> it done.
>  Sharing my experiences as Novice through Expert the biggest hurdles
> are: 1) Know how to use your EDA tool: properly convert from SCH to PCB,
> accurate use of constraints to auto-route a majority of your board. know
> how to use tools for Pre & Post Analysis, accurately flag design rule
> violations so they don't reach production and knowing when SI analysis is
> needed is critical to doing a layout. Without these, items 2 to 5 below
> pale in comparison.  2) Vendor Selection: I've seen too many companies bid
> on every PCB design and Fab. Don't piss off your vendors by having vendors
> bid on each and every design. Not only is this a ridiculous waste of time
> for all the vendors and the Engineers it really pisses our vendors off.
> Picking the cheapest vendor usually results in unforeseen NRE, design and
> manufacturing variations that may cost you greatly. I've seen companies
> fail from this mistake alone because vendors eventually refuse to service
> or jack their prices up.
> GOAL: Establish an Approve Vendor List and stick with them.   3) William,
> you nailed it on the Footprints (ie., Land Patterns). Those are hideous and
> extremely time consuming. But that's where companies that build libraries
> that follow IPC standards can share some of the burden. The only one I know
> of is PCB Libraries but I am sure there are others (???).
> Once the tools have been mastered and library footprints are no longer
> that difficult of a task .... 4) The next biggest hurdle are changes to the
> design and subsequently the Bill of Material. Because this usually involves
> adding -- not removing -- components this can result in the need to start
> the layout from scratch ... especially for extremely dense designs. My
> secret to high density boards when I know changes will come ... is to use
> larger then necessary components. If the design calls for a 0805 CAP use a
> 1206 instead. There are many other tricks.
> 5) Of course, dotting the i's and crossing the t's (i.e, documentation) is
> a huge part of the design but with the many improvements from our EDA
> suppliers this is becoming significantly less of a burden.  6) Of course
> the biggest time consuming headache is when failed to properly design trace
> lengths and Power Planes and the boards fail. I tried to keep this
> short. Thanks for the opportunity to share.
>  Dave
>       From: "Brooks, William" <[log in to unmask]>
>  To: [log in to unmask]
>  Sent: Thursday, September 10, 2015 12:04 PM
>  Subject: Re: [DC] Estimating PCB Design time
>
> Regarding design time... What PCB design activities seem to be time
> adders? What makes you work harder to get the job done? What slows you
> down? What gets in your way?
>
> Typically the things that seem to take my time are related to doing
> verification of components and building of footprints and symbols for the
> cad tool. This activity seems to have a great risk associated with it... so
> it needs my attention... Errors in the footprint or symbol can propagate to
> other designs if they go undetected... drive re-spins of the board and
> assembly... and ultimately delay time to market.
>
> Communication between the design team members also can affect the success
> of the design...
>
> Also design changes due to overlooked issues... Checking... placement,
> routing... ?
>
> What do you see as a time consuming activity or higher risk activity in
> your designs? How do you alleviate these issues?
>
> Thanks, I'm looking forward to your responses... :)
>
>
>
>
> William Brooks, CID+
> Printed Circuit Designer
> 2747 Loker Ave West
> Carlsbad, CA 92010-6603
> 760-930-7212
> Fax:        760.918.8332
> Mobile:    760.216.0170
> E-mail:    [log in to unmask]
>
>
>
>
>
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-- 
----------------------------------------------
Gary A. Crowell Sr., P.E. <http://www.ipels.idaho.gov/>, CID+
<http://dc.ipc.org/html/default.htm>
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