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April 2015

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Subject:
From:
SALA GABRIELE <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, SALA GABRIELE <[log in to unmask]>
Date:
Wed, 1 Apr 2015 15:10:46 +0200
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Hi Dave,

the following IPCs, also can give you useful information:

- IPC-7095C Design and Assembly Process Implementation for BGAs

- IPC-7093  Design and Assembly Process Implementation for Bottom
Termination Components (QFN,DFN,SON, LGA,MLP, etc

- IPC-7094 Design Assembly Process Implementation for Flip Chip and Die Size

      Components

Gabriele

-----Messaggio originale-----
Da: TechNet [mailto:[log in to unmask]] Per conto di David Hillman
Inviato: martedì 31 marzo 2015 23.50
A: [log in to unmask]
Oggetto: [TN] Package Definition

Hi folks - does anyone know if JEDEC (or some other industry association)
have a industry recognized definition of  Ball Grid Array,  Chip Scale
Package and  Flip Chip style packages? I am looking for some standard or
specification that defines these packages as package styles/types.

Dave Hillman
Rockwell Collins
[log in to unmask]


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