At 12:52 PM 4/24/2015, Steven Kelly wrote:
>Hi Dwight,
>OK - these have to be button/selective plated - ever seen that?

sure. daily. a sizeable minority of ~1300 layouts/year.

>And we
>have to etch .004 spaces after the button plate.

That's pretty routine in the upper tiers of the 
US and European pwb fab industry with 
immersion/electroless outerlayer finishes.  If 
that outerlayer is finished with hard 
(electrolytic) gold finish then you'll likely 
need to keep it to 4.5 to 5 mil min spacing.

If this is volume design to be built in a 
commoditized environment (offshore) then the 
answer changes and the constraints are 
different.  If an offshore uVia fab then probably 
get it though they will likely panel plate again 
and planarize (not button plate). .
If a commodity pure PTH fab offshore then they 
are unlikely to have any via fill capability 
whatsoever (s/m plugging yes, via fill no).

>Regards Steve
>
>On 2015-04-24, 3:30 PM, "Dwight Mattix" <[log in to unmask]> wrote:
>
> >if you're at the right fab, that can be solid
> >copper filled (plated full).  We see a lot of
> >that used, esp in "core" vias in 2n2 and 3n3 uVia stackups.
> >
> >A lot of extreme aspect ratio Loadboard and
> >Probecard designs use 5 and 6 mil flipdrilled
> >thru vias as thick as 5mm overall. Those finish
> >after plating in 3-4 mil range at the knee.
> >Those (very) select few shops that can fill those
> >plated vias up beyond 30:1 aspect ratio with the
> >likes of San-Ei and then overplate for socket or probe contacts.
> >
> >At 07:13 AM 4/23/2015, Steven Kelly wrote:
> >>Hi All,
> >>Do you think it is feasible to do non-conductive
> >>via fill on a .0025- .003 finished hole size ¡©
> >>overall thickness is .028. Regards Steve
> >>
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