Hello Brian,

Galvanic corrosion can occur during board manufacturing in the plating processes that are used to plate immersion silver or immersion tin finishes.  This is especially a concern where solder mask has been undercut creating a crevice where the plating chemistry becomes trapped.  The immersion silver or tin plating processes do not use electricity, but the chemistry is formulated to etch copper while plating silver or tin.  The plating chemistry that is trapped in a solder mask crevice has the potential to react aggressively with the copper creating an accelerated copper etching effect.  

I have seen cases where over 0.5 mils of copper has been etched away during immersion tin plating.  That much reduction in a copper thickness is certainly a cause for concern and poses a reliability issue.  

This type of aggravated copper corrosion can be prevented through proper control of the chemistry in the plating process.  The solder mask coating process can also be controlled to minimize undercut, which reduces the possibility of this issue occurring.   

Changing the circuit design to include a teardrop shape is one way to help ensure that a good electrical connection still exists if the aggravated copper corrosion issue occurred.  


Best regards,

Tony Lentz

FCT Assembly
Field Application
[log in to unmask]
970-566-0360 Mobile

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brian Ellis
Sent: Thursday, April 23, 2015 9:37 AM
To: [log in to unmask]
Subject: Re: [TN] Teardrops (Cu trace expansion) on thin traces - needed for OSP?

I don't believe that it is an urban myth. I thought that I had explored this in my book, but I may be mistaken as I cannot find it! I believe that the problem is due to the capillary action retaining etchant in the acute angle. The minute quantity of etchant would quickly become exhausted, possibly leaving poorly soluble precipitates in the "corner" 
as the pH dropped (alkaline etchant) or increased (acid etchant). 
However, this explanation is possibly speculative.

On 23/04/2015 18:01, Wayne Thayer wrote:
> Is that crevice corrosion during board fab, or during service life? 
> For years, I've been wondering what the "acute angle" avoidance issue 
> was and where it came from. Every time I put in an acute angle, it 
> gets under-etched because the photomask makes it hard to get etchant 
> into the tip of the notch, so I've been ignoring that rule as either 
> an anachronism from some etching process used in the 60's or just an urban myth.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of David Hillman
> Sent: Thursday, April 23, 2015 10:48 AM
> To: [log in to unmask]
> Subject: Re: [TN] Teardrops (Cu trace expansion) on thin traces - 
> needed for OSP?
>
> Hi folks - the problem isn't so much a galvanic corrosion issue but 
> really a crevice corrosion issue coupled with plating bath parameter 
> control. The NASA DoD Lead-free Solder Consortia experienced this 
> issue on a number of its test vehicles. The problem primarily impacts 
> plated thru hole technology but has been also observed with surface 
> mount technology. Using teardrop shaped pads gives the board 
> fabricator a bit more process robustness. I haven't seen much 
> publication of this issue yet in the public domain but it is a known 
> issue in the industry for folks using immersion silver surface 
> finishes. Details on this issue were documented in the NASA DoD Lead-free Solder Consortia final report.
>
>
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
> On Thu, Apr 23, 2015 at 9:29 AM, Brian Ellis <[log in to unmask]> wrote:
>
>> The likelihood of electrolytic corrosion on a silver/copper couple is 
>> really negligible, because the EMF difference is only 0.485 V, 
>> referred to hydrogen equals 0 V. This is insufficient to dissociate 
>> most ions.
>>
>> On 23/04/2015 15:59, MacFadden, Todd wrote:
>>
>>> Hello Technet friends,
>>>
>>> We are usually asked by our PCB suppliers to add teardrops (track
>>> expansion) to thin traces (<=5mil) at soldermask openings. We 
>>> understand the impetus for this on immersion silver boards, where 
>>> there is a risk of galvanic corrosion due to Cu-Ag couple at the 
>>> soldermask/Cu interface of SMT pads.
>>>
>>> But some suppliers also ask for track expansion on OSP boards. What 
>>> would be the motivation in this case? My understanding is the risk 
>>> of corrosion at the soldermask interface on OSP boards is low, even 
>>> if the soldermask undercut is severe. So is there perhaps some other 
>>> reliability advantage to having wider copper at trace/pad interfaces 
>>> on otherwise thin traces? Do others get this question as well?
>>>
>>> Thanks in advance for any thoughts or insight.
>>>
>>> Todd MacFadden
>>>
>>>
>>>
>>>
>>>
>>>
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