Hi folks - the problem isn't so much a galvanic corrosion issue but really
a crevice corrosion issue coupled with plating bath parameter control. The
NASA DoD Lead-free Solder Consortia experienced this issue on a number of
its test vehicles. The problem primarily impacts plated thru hole
technology but has been also observed with surface mount technology. Using
teardrop shaped pads gives the board fabricator a bit more process
robustness. I haven't seen much publication of this issue yet in the public
domain but it is a known issue in the industry for folks using immersion
silver surface finishes. Details on this issue were documented in the NASA
DoD Lead-free Solder Consortia final report.



Dave Hillman
Rockwell Collins
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On Thu, Apr 23, 2015 at 9:29 AM, Brian Ellis <[log in to unmask]> wrote:

> The likelihood of electrolytic corrosion on a silver/copper couple is
> really negligible, because the EMF difference is only 0.485 V, referred to
> hydrogen equals 0 V. This is insufficient to dissociate most ions.
>
> On 23/04/2015 15:59, MacFadden, Todd wrote:
>
>> Hello Technet friends,
>>
>> We are usually asked by our PCB suppliers to add teardrops (track
>> expansion) to thin traces (<=5mil) at soldermask openings. We understand
>> the impetus for this on immersion silver boards, where there is a risk of
>> galvanic corrosion due to Cu-Ag couple at the soldermask/Cu interface of
>> SMT pads.
>>
>> But some suppliers also ask for track expansion on OSP boards. What would
>> be the motivation in this case? My understanding is the risk of corrosion
>> at the soldermask interface on OSP boards is low, even if the soldermask
>> undercut is severe. So is there perhaps some other reliability advantage to
>> having wider copper at trace/pad interfaces on otherwise thin traces? Do
>> others get this question as well?
>>
>> Thanks in advance for any thoughts or insight.
>>
>> Todd MacFadden
>>
>>
>>
>>
>>
>>
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