Quoted for truth:
"It all boils down to what the designer and the customer require for
full functionality and whatever level of reliability limitations they
can live with (or not)."
The capability will vary depending on fabricator and when or how the
tooling hole is drilled.
Generally, tooling holes drilled at secondary will have tighter
tolerance capability than those drilled at primary. +/- 75um
position is common
Tooling holes drilled with a precision (CCD aligned) drill will have
an even tighter tolerance capability. +/- 50um position is common
Tooling holes laser milled have ability to achieve even tighter
tolerances relative to the outerlayer pattern. +/- 25um position is
routinely required for sockets and probeheads at .4mm pitch and below.
+/-13um requirements are showing up for direct probe cards but don't
go spec'ing that just yet. ;^) Good luck finding a pwb fab with the
gauge capability to prove it (let alone the process capability --
it's a pretty narrow field).
We place a lot of sockets and probe heads for fine pitch devices
that are located with a hole and slot.
At 07:49 AM 4/21/2015, Stadem, Richard D. wrote:
>Outside of what Wayne discussed (and a good posting it was!), for
>other feature's tolerance, I don't think there is any hard and fast
>requirement in the standards. The rest of the tolerances are
>controlled by the fabrication drawing for the PWB and can vary
>according to the design. This would include dimensional tolerances
>for locations of drilled holes with respect to X, Y datum reference
>points (as specified in the drill table on the PWB fab drawing),
>fiducials, artwork, etc. For a Class 1 PWB the tolerances might be
>much more than those for a Class 3, but even then not necessarily
>so. It all boils down to what the designer and the customer require
>for full functionality and whatever level of reliability limitations
>they can live with (or not).
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Cables, Tim
>Sent: Tuesday, April 21, 2015 9:16 AM
>To: [log in to unmask]
>Subject: Re: [TN] Tooling hole to Artwork tolerance
>
>Thanks, Wayne,
> If anyone has any other thoughts on this please comment.
>Regards
>Tim Cables
>PCB Design
>
>Aclara
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Wayne Thayer
>Sent: Tuesday, April 21, 2015 10:05 AM
>To: [log in to unmask]
>Subject: Re: [TN] Tooling hole to Artwork tolerance
>
>Hi Tim-
>
>This is a derived specification. The PCB fabricators understand this
>as requirements on the annular ring of a drilled and plated through
>hole. Look up stuff related to "break-out". I think Class 2 requires
>no more than 90% breakout, but many customers separately specify
>"NBO" for No BreakOut.
>There's really not much of a difference between these if you're a
>fabricator, as long as "teardrops" or "snowmen" are allowed on the artwork.
>
>Anyway, the breakout spec controls the total mis-alignment between
>the drilling process and final conductor formation process (be that
>etching or additive plating). If the tolling holes/artwork are too
>mis-aligned, the fabricator won't make the breakout spec.
>
>Sophisticated board designers know this inherently, so if they want
>a board to have high accuracy of artwork to tooling holes, they'll
>have some plated through holes with whatever minimum annular ring
>the PCB fabricator will commit to.
>
>Wayne Thayer
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Cables, Tim
>Sent: Tuesday, April 21, 2015 9:46 AM
>To: [log in to unmask]
>Subject: [TN] Tooling hole to Artwork tolerance
>
>Can anyone tell me what the IPC spec is for this and which standard
>it is listed in?
>
>
>Tim
>
>
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