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From:
Yuan-chia Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Yuan-chia Joyce Koo <[log in to unmask]>
Date:
Wed, 11 Mar 2015 22:00:51 -0400
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nice.  thx Jack... can't believe ipc is getting into std that are  
down to the details without design specific - for example, power/ 
ground with thermal path are difficult to solder due to the heat  
sinking capability that design to it.  how could you demand hole fill 
% in relation to the signal?  unless you do at design level for  
overall layout assessment... I am sure the surface ground vs internal  
ground are different behavior in term of soldering.... good to know  
ipc leave it open... (designer need to sign on to his/her design...  
not just hiding behind the ipc std... same goes to the Contract  
MFG... design review still a must, not just CAD dwg check by  
computer... ) my 1.56 cents-- less value everyday... getting old.

thanks for the detail update..
             jk
On Mar 10, 2015, at 1:37 PM, Jack Olson wrote:

> Greetings,
> Before my recent trip to San Diego for the IPC CONFERENCE and APEX/ 
> EXPO
> fades to a dim memory, I thought I would share my experience with  
> those of
> you who couldn't attend. (since we have had shrinking travel  
> budgets, I
> always appreciate hearing from YOU if I can't make it to something)
> So, most of my involvement was in the IPC Standards Development  
> Committee
> Meetings, and here's a synopsis of the ones I attended:
> (apologies in advance if I misunderstood or misrepresented anything.
> Sometimes I still feel like "the new guy" during these discussions)
>
> J-STD-001/IPC-A-610 SYNERGY MEETING (Saturday 8:00-5:00) This  
> meeting works
> to resolve discrepancies between the Requirements for Soldered  
> Electrical
> and Electronic Assemblies (J-STD-001) and the Acceptability of  
> Electronic
> Assemblies standard (IPC-A-610).
> -
> The committee discussed the "void criteria" in Table 7-16 for  
> components
> with non-collapsible solder balls. There is not enough data  
> available to
> support a decision either way, so the committee was proposing to  
> add the
> text "void criteria will be established between user and supplier".  
> There
> were arguments against this, because it could create "action items"  
> for
> many companies to establish acceptability criteria for voids with its
> suppliers. The committee voted to accept the text “void criteria is  
> not
> established.”
> -
> Solder “Vertical Fill” Requirement (IPC-A-610 Table 7-4) One of the  
> longest
> discussions was determining the solder filling requirement for  
> plated holes
> per . The committee was considering relaxing the requirement for  
> designs
> with copper planes (or for holes connected to thermal planes),  
> because of
> the difficulty of getting solder to fill the hole.
> Maybe this example will illuminate the important points of the  
> discussion:
> Let's say we specify a 2-pin through-hole connector in a design as a
> "power" connector, one pin connected to a power plane and the other  
> to a
> ground plane. Now suppose we specify another 2-pin connector in the  
> same
> design as a "sensor" connector, with signal connections (neither  
> pin tied
> to a plane). Now, if the soldering requirements are relaxed for holes
> connected to thermal planes, the question will immediately be  
> asked, "Why
> does my Sensor Connector have to be soldered BETTER than my Power
> Connector?" It doesn't make sense. If the relaxed requirement is  
> acceptable
> for one, it should be acceptable for the other, and the very next  
> proposal
> will be to relax the requirement for ALL soldered holes. The  
> committee is
> not prepared to accept that yet without reliability data to support  
> the
> change.
> On the other side of the discussion, suppose we are specifying a 70- 
> pin
> Through-Hole connector and we decide to connect all of the unused  
> pins to
> the ground plane. As long as the mechanical strength of the  
> connection is
> not compromised and the electrical connection is maintained through- 
> out our
> worst-case scenarios (extreme thermal cycling, for example) do we  
> really
> care if those holes are completely filled with solder?
> I don't think this issue has been fully resolved by IPC, but for  
> now, the
> proposal to change the requirements for designs with thermal planes  
> was
> REJECTED.
> -
> Board Edge Delamination (J-STD-001 9.1.3, IPC-A-610 10.2.5) The  
> committee
> resolved a discrepancy between the way edge delamination criteria was
> stated in the two documents. If I understood correctly, one document
> declares a reject if the delamination is greater than 50% of the  
> distance
> to the nearest conductor or GREATER THAN 0.1 inches from the board  
> edge.
> The other document
> declares a reject if the delamination is greater than 50% of the  
> distance
> to the nearest conductor or
> WITHIN 0.1 inches of the conductor. The committee voted for the second
> option.
>
> IPC-6012 / IPC-A-600 BARE BOARD ACCEPTABILITY (Sunday 8:00-5:00)
> Copper Wrap Requirement (IPC-6012 Table 3-4)
> The committee had proposed changing the wrap requirement from 500
> micro-inches to 200 microinches. The document is falling behind  
> current
> manufacturing practices (it has been reported that 80% of high density
> board designs are being fabricated at 200 with written waivers or
> exceptions to the requirement), but several negative votes have been
> submitted against the proposed standard for ballot.
> I think Don Dupriest's point was that many of his products had  
> specifically
> been designed for enough clearance to maintain the 500 requirement,  
> and by
> changing the standard, he wouldn’t be able to prevent fabricators from
> building to 200 without revising the procurement documentation. Others
> expressed reluctance based on the lack of reliability data, so the
> committee voted to retain the 500 specification for now. This  
> brought up
> another discussion related to legacy data, below:
> -
> “Cut-In” dates to preserve Legacy Product Requirements:
> The traditional method of calling out IPC standards on drawings is  
> to use
> the document number WITHOUT the revision letter. A specification  
> that uses
> a document number without its revision level is always assumed to be
> “whatever the latest revision is”. That way, the product can be
> manufactured using the latest industry standards without having to  
> revise
> the drawings or other procurement documentation.
> The IPC is entertaining the idea of using “cut-in dates” in certain
> situations to allow fabricators to “catch up” to the latest  
> publications.
> For example, the committee that maintains the IPC-4101  
> “Specification for
> Base Materials” is implementing this concept to allow laminate
> manufacturers a certain amount of time to use up their existing  
> materials
> before the new specification goes into effect on the cut-in date.
> -
> Micro-section Preparation
> There were two ways of interpreting the tolerance for preparing
> micro-section samples for quality control inspection, related to the
> acceptable amount that the section can be off-center. The  
> specification
> allows 10%, but it is not clear how to determine the 10% tolerance.  
> Is it
> 10% of the distance away from the true center of the hole? or is it  
> that
> the measurement from side to side can’t be more than 10% less than  
> the true
> diameter of the hole? After a lengthy discussion, the committee  
> voted to
> measure the diameter, which is more definitive than trying to  
> measure the
> depth of the "grinding zone", but this method allows a greater  
> margin of
> error.
>
> DESIGNER DAY (Monday 7:30-1:00)
> This was a series of short presentations on topics of interest to  
> circuit
> board designers.
> - Planning for Design Success - Carl Schattke, Tesla Motors
> - Component Mounting Issues and Recommendations - Rainer Taube, Taube
> Electronic GmbH and FED
> - Surface Mount Design and Land Pattern - Tom Hausherr, CID+  
> President, PCB
> Libraries, Inc.
> - Successful Communication with Cross-Cultural Teams - Stephen  
> Chavez, CID+
> UTC Aerospace Systems
> - Success Through Control of Cost and Quality - Rick Hartley,  
> retired from
> L-3 Communications
>
> IPC-2152 CURRENT CARRYING CAPACITY (Monday 3:00-5:00)
> The initial release of IPC-2152 has been out for a few years now,  
> and the
> IPC has not received any negative feedback regarding the data or  
> advice it
> provides (no news is good news?). A survey was created to collect user
> feedback, and to help set a direction for the next steps in the  
> evolution
> of the document. The summary highlighted three areas for further  
> study;
> 1) study the combined effect of current through parallel traces
> 2) study the thermal performance of vias
> 3) study the performance of flexible circuits
> A test board design was proposed that would be useful for items 1)  
> and 3),
> and the fact that this design could also be used to test pulses and  
> current
> spikes was discussed. FTG offered to make the test vehicle circuit  
> boards
> for the committee.
> Oh, almost forgot to mention this; The document/committee name is  
> being
> changed from "Current Carrying Capacity" to "Thermal Management"
>
> KEYNOTE – THE XBOX STORY (Tuesday 8:00-10:00)
> Robbie Bach, former President of Entertainment & Devices at  
> Microsoft, gave
> an interesting presentation about “The Xbox Story: Lessons in  
> Strategy,
> Team Management and Entrepreneurship”. He started out talking about  
> goals
> and the benefit of focusing a group mission into one sentence. For
> examples, Microsoft’s ”put a computer on every desk in every home  
> running
> Microsoft software”, and Sonos’ “bring all the music in the world into
> every room of your house” (paraphrase). But the concept that  
> impressed me
> the most was that when Microsoft had the “Red Ring of Death”  
> disaster that
> cost them over a $BILLION to recover from, their Customer Approval  
> rating
> actually INCREASED during that time because of the way they handled it
> (extending warranty to 3 years, no-hassle return policy, etc.)  
> Great Talk!
>
> IPC-2221/2222 PRINTED BOARD DESIGN STANDARD (Tuesday 10:00-5:00)
> At one point in time the IPC had considered adding all of the Design
> Guidelines for HDI into IPC-2222 (Design Standard for Rigid  
> Boards), but it
> has been decided that there is too much specific information for  
> HDI, and
> they will continue to retain that information in the sectional  
> document
> IPC-2226 (Sectional Design Standard for High Density Interconnect).  
> This
> document was originally released in 2003 and needs a significant  
> update, as
> the technology has changed so much since then. The committee  
> addressed some
> of the initial suggestions and assigned sub-groups to review and  
> revise
> some of the data in the Tables.
>
> SHOW FLOOR RECEPTION (Tuesday 5:00-6:00)
> I was busy in meetings most of the day so I didn't invest much time  
> on the
> Exhibition floor, but one of the more interesting technologies I  
> saw was
> eSurface, which is a new process for creating very thin traces with  
> strong
> peel strength and tight tolerance. One mil trace/space geometries  
> are now
> routinely being manufactured at Murietta Circuits in Anaheim, CA.  
> Here's
> How:
> http://esurface.com/the-esurface-manufacturing-process-steps/
> Here's a collection of Photos and Videos from the exhibition floor  
> hosted
> by "RealTime with... IPC"
> http://realtimewith.com/rtwboot/show.php?id=81
>
> IPC-7351 LAND PATTERN STANDARD and IPC-7070 COMPONENT MOUNTING (Wed
> 8:00-12:00)
> The IPC is reviving the old IPC-CM-770 Component Mounting Guideline  
> (1996?)
> and after a complete rewrite it will be assigned to number  
> IPC-7070, which
> will conform to the newer document naming convention. Rainer Taube is
> leading this effort. He will be collaborating with Tom Hausherr who is
> heading up a significant revision to IPC-7351 (Land Patterns). The
> committee voted to rename IPC-7351 from a “Land Pattern Standard” to a
> “Land Pattern Guideline”, since there is so much variance in land  
> pattern
> dimensions currently being used in the industry. Some of the more  
> drastic
> changes in IPC-7351 is to move most of the component mounting  
> information
> to IPC-7070, to recommend “rounded rectangle” shapes over  
> “rectangle” in
> many families, especially for RoHS compatible designs (paste screening
> process doesn’t like sharp corners anyway, harder to “release”, less
> wetting in reflow leaves exposed copper corners, corners don’t  
> contribute
> to solder joint reliability anyway). Another change is that  
> companies are
> starting to realize that all the silkscreen ink underneath  
> components is
> just a waste of ink, not useful to anyone and in many cases  
> contributes to
> soldering defects because small components can’t settle into molten  
> solder
> if they are riding on a silkscreen line (think of a “teeter-totter”  
> on a
> playground). The three-tier system based on design density is being  
> removed
> from several families of components, in favor of recommending a  
> “best” or
> “proportional” solder joint dimension. Also, the “rectangular  
> courtyard”
> system is being replaced by courtyards that more closely match the
> component body size to allow better placement strategies that won’t  
> look
> like errors to CAD rule-checking systems.
>
> IPC-7093 BOTTOM TERMINATION COMPONENTS (Wednesday 1:30-3:00)
> The committee discussed a new etching technology that would expose  
> part of
> the side wall of the termination to the plating process, which  
> would make a
> partial side fillet, making automated optical inspection more  
> reliable.
> Also discussed window-pane techniques for the thermal pad solder  
> stencil
> and negative values in Table 6-1.
> One interesting point that came up was that Table 6-1 in 7093 is  
> identical
> to Table 3-1 in 7351. It wasn't clear who copied from who, so now  
> if that
> table needs to be revised, who owns it? and who prevents them from  
> becoming
> out of sync with each other? Maybe we need some kind of digital  
> "links"
> when documents are borrowing from each other?
>
> TRIBUTE TO DIETER BERGMAN (Wednesday 6:30-8:30)
> Dieter Bergman joined the IPC in 1962, became chairman of the IPC  
> Design
> Committee in 1968, was elected Chairman of the IPC Technical  
> Activities
> Executive Committee in 1974, and then became the IPC Technical  
> Director.
> Known as “the man who would take 45 minutes to answer a 10-second
> question”, my personal experience was that he and Gary Ferrari came to
> California to present the new IPC-STD-275 Design Standard to us  
> sometime in
> the late 80’s, planted the seed that we could all benefit from
> collaboration, and encouraged us to work towards creating a common
> foundation for everyone to build upon. That Design Standard  
> energized our
> PCAD User Group, and I’m still involved to this day because of his
> inspiration. Thanks, Dieter… R.I.P.
>
> Oh, I suppose I should mention some
> CELEBRATIONS!
> Gary Ferrari is our newest IPC HALL OF FAME member! (He taught me  
> CID+, and
> I am so happy that he has been recognized for his work)
> Oh, and eight people received Dieter Bergman Memorial Scholarships:
> Don Dupriest, Denny Fritz, Dave Hillman, Bernie Kessler, Bob Neves,  
> Ray
> Prasad, Randy Reed and Doug Sober
> and my friend Kelly Dack became an IPC certified Trainer at the  
> conference,
> successfully completing his first CID class, monitored by Gary. Way  
> to go,
> Kelly!
> Now we have 17 new CID members!!
> and we also have 10 new CID+ members, taught by Paul Fleming!!!
> and I got to eat ice cream with Bernie Kessler!!!!
>
> ok, when I get to the quadruple exclamation points, I realize I  
> need to
> fade away for awhile. In summary, even though I was there for 6 days I
> still feel like I missed a lot. Hope this helps those of you who  
> could not
> attend this year.
>
> Jack (aka "the new guy")
>
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