All:

I think the second sentence in 3.6.2.16 is as close as you could get to calling the initial picture sent by Russ a rejectable condition.  The void appears to be just deeper than .003".  (Screenshot attached for convenience.)

This is assuming that what we are looking at in the original picture is a true void (located above the resin fill and below the cap) caused by non-conductive holefill not making it into the via like it should have.

Unfortunately whether or not a void of that size, at that location, surrounded by that amount of copper poses a real reliability concern is probably outside of the current scope.  One would think that if thermal stress did not cause it to rupture, is there some other sort of long term risk?

Jeff

-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Pete Menuez
Sent: Wednesday, March 25, 2015 12:51 PM
To: [log in to unmask]
Subject: Re: [IPC-600-6012] Cap Plating - Separation, dimple, void or acceptable?

All:

I don't agree with the 'plating separation' call. The plating did not separate.  There is a void in the via fill and the electroless copper coated the void and it was subsequently plated.  I think the correct evaluation would be paragraph 3.6.2.11.2 and the referenced paragraphs.

Pete

-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Russ Shepherd
Sent: Wednesday, March 25, 2015 1:16 PM
To: [log in to unmask]
Subject: Re: [IPC-600-6012] Cap Plating - Separation, dimple, void or acceptable?

We would normally call it plating separation, therefore non-conforming as well.  I am getting some pushback, especially if it is solid fill material (no gap), similar to an inclusion, and plating thicknesses are met.

Russ

-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Chris Mahanna
Sent: Wednesday, March 25, 2015 9:39 AM
To: [log in to unmask]
Subject: Re: [IPC-600-6012] Cap Plating - Separation, dimple, void or acceptable?

We call it nonconforming for separation, as the design activity likely envisioned it as plated together.
Limitations need to be placed upon any caveat, as it can encroach onto the surface, and it interplays with external registration requirements.
There was a small group of people working on a proposal for 6012D, but it got moved down the list.

Robisan is currently in the middle of some program disagreement on this issue too.
We have been stalling (leaving it as nonconforming), in an attempt to make sure design activities have reviewed, understand and limit the caveats.

If 6012 can take it up quickly, maybe we can find an industry standard answer.

Chris


Chris Mahanna
Robisan Laboratory Inc.



-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Russ Shepherd
Sent: Wednesday, March 25, 2015 12:23 PM
To: [log in to unmask]
Subject: [IPC-600-6012] Cap Plating - Separation, dimple, void or acceptable?

Hello all,

I have been coming across a condition lately that many board suppliers are saying is unavoidable.  The condition in the picture attached where there is more than one cap plating process with a hole fill (of other holes) in between.  What's happening ins there is a deposit of fill material on the surface of the first cap plating layer getting covered by the second cap plating process.  How does this get addressed?  As an inclusion, separation, dimple, plating void, or non-issue?

[cid:[log in to unmask]]

Thanks!


Sincerely,

Russ Shepherd
Vice President of Operations
MICROTEK LABORATORIES
(714) 999-1616
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