ask your part vendor.  they know the internal structure and cap wafer  
based on the design tolerance... no body else can tell you better  
than your vendor.  remember, the wlp usually use single crystal as  
cap, if you have crack/chip, depend upon the stress level during your  
process and user environment, it might propagate.  my 2 cents.
       jk

On Dec 23, 2014, at 12:09 PM, Evamaria Jones wrote:

> Does anyone know of acceptability requirements regarding chipped /  
> component damage on chip scale and wafer level packages? How much  
> chipping of edges are acceptable on the exposed silicone  
> die? ...and can minor chipping of the silicon substrate cause  
> performance problems? Is the silicon die considered the component  
> substrate or package? IPC-A-610E, 9.3 states that chipped or  
> cracked component substrate constitute a defect. Clearly a crack or  
> chip that extends from top to bottom would be defect. Would 1/4mm  
> chip on top be a defect. Any guidance would be appreciated.
> Eva J


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