Does anyone know of acceptability requirements regarding chipped / component damage on chip scale and wafer level packages? How much chipping of edges are acceptable on the exposed silicone die? ...and can minor chipping of the silicon substrate cause performance problems? Is the silicon die considered the component substrate or package? IPC-A-610E, 9.3 states that chipped or cracked component substrate constitute a defect. Clearly a crack or chip that extends from top to bottom would be defect. Would 1/4mm chip on top be a defect. Any guidance would be appreciated.
Eva J