Silicon is brittle and fragile so dicing can easily cause chipping and cracking.  Information in MIL-STD-883G METHOD 2010.1.1 starting from 3.1.3 and other similar specifications have defined inspection and rejection criteria. Some of these documents are available to download free online.

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From: TechNet [mailto:[log in to unmask]] On Behalf Of Evamaria Jones
Sent: Tuesday, December 23, 2014 11:10 AM
To: [log in to unmask]
Subject: [TN] Wafer level package or Chip scale package component damage

Does anyone know of acceptability requirements regarding chipped / component damage on chip scale and wafer level packages? How much chipping of edges are acceptable on the exposed silicone die? ...and can minor chipping of the silicon substrate cause performance problems? Is the silicon die considered the component substrate or package? IPC-A-610E, 9.3 states that chipped or cracked component substrate constitute a defect. Clearly a crack or chip that extends from top to bottom would be defect. Would 1/4mm chip on top be a defect. Any guidance would be appreciated.
Eva J

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