Phil,
From a practical point of view, you are dealing with a hard encapsulant at
80D. Now then, we don't know how heavily filled it is, nor what it is
filled with, so we don't fully know its expansion properties. We don't know
if it is silicone based, or epoxy. Temp cycle conditions are also an
unknown.
My caution to you, over and above those already made relative to the
potential CTE mismatches involved, is that if you are going to pot the
solder joints that you need to make absolutely sure that the entire joint is
totally surrounded by the encapsulant. That means under the components as
well!
I have observed partially encapsulated joints 'extruding' solder out of the
non-surrounded side [under a chip resistor] as a result of temp cycle.
I've also observed this on flip chip joints that had a void in the underfill
immediately adjacent to the bump. Eventually, the solder will 'extrude'
into the void as a result of the stress imposed by its own expansion and the
expansive properties of the encapsulant. It moves where there is less
resistance - into the void [or in the case of a chip capacitor/resistor -
under the component!
So the short form suggestion would be to make sure all flux is removed from
under the components, and make sure the assembly is well de-aired during
potting.
The more benign the use environment, the less of a problem this is, but as
Joyce indicated I would also look for a lower temp alternate cure.
FWIW
Steve Creswick
Sr Associate - Balanced Enterprise Solutions
http://www.linkedin.com/in/stevencreswick
616 834 1883
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Nutting, Phil
Sent: Wednesday, July 09, 2014 9:05 AM
To: [log in to unmask]
Subject: Re: [TN] High cure temp for potting electronics
My concern would be the Tce differences between the potting, flex board and
components. I would also want to cycle the temperature at least 10 degrees
above and below the "operating points" for an extended period of time. More
concern as the amount of potting increases. In a large potted filament
assembly we had failures when the epoxy shrank during curing and would crack
the ferrite cores.
For an application of a feedthru which always leaked with a hard epoxy we
switched to an epoxy that actually felt "soft" once cured. Leaks solved.
Phil
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Mike Fenner
Sent: Wednesday, July 09, 2014 5:10 AM
To: [log in to unmask]
Subject: Re: [TN] High cure temp for potting electronics
150C for 2 hour might well affect the grain structure of the solder, but
what cycling the product sees in service may also affect it. Cycling means
not just max and min temps but also the rate of change to/from and how long
at each max/min. Thus after say 1000 hours of in-service use the grain
structure of the solder could be very different from as made. In this
context the 2 hours initial 150C may not have made any difference to the
effect of the cumulative in-service exposures. You start from a different
place that's all.
A good example in the public domain (if you can still find it) is the
difference between vapour phase reflow and forced convection. Protagonists
for forced convection argued that the grain structure from VPR was coarser
than forced convection and therefore was inferior. They were correct on
initial grain structure, but in use the solder joints cycled to the same
state after a few hundred hours. I recall the work was done by Nokia, but
can't give you specific reference.
I think this explanation is what happens when you try to avoid an "it
depends", but you can see that it does. In the olden days we would have said
suck it and see, in the not so olden days, we would have done a series of
empirical tests. Now you would make a DoE. The potting compound would alter
the stresses on solder of course, so it probably is slightly academic what
happens to solder joints alone as you really need to know what happens to
the whole assembly. See below.
Regards
Mike
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Yuan-chia Joyce Koo
Sent: Wednesday, July 09, 2014 1:09 AM
To: [log in to unmask]
Subject: Re: [TN] High cure temp for potting electronics
I am also echo with Roger's caution:
(1) if the flex is using acrylic as bonding layer, you might see degradation
of adhesion.
(2) not all polyimide tape made equal, some may or may not withstand 150C
for dimensional stability.
(3) grain growth sure will happen at 150 C for 2 hr if you use eutectic
Pb/Sn solder - how much impact on your reliability? you need good data or
calculation based on user environment
(4) 150C cure for 2 hr are common for chip potting, normally there is
alternative cure, like 130 C for 6 hr, you need to know what is the curing
mechanism, what kind of activator, one stage or two stage cure. 130 C
possibly more feasible for flex (again, if your adhesion layer is polyimide
based, it should be fine).
(5) you need hard data to find out the cure and CTE in relation to your chip
- as mentioned by Roger, you need to be careful (you can pull out of a wire
bond if it thermal shocked - due to poor selection of material. your design
group should be the one (a) select material, and (b) dictate the process how
to apply the material and
(c) ensure achieve the reliability for the design intend... ).
my 2 cents.
joyce
On Jul 8, 2014, at 5:59 PM, Roger Mack wrote:
> my concern would be the properties of the potting, not the solder
> joints.
> Elevated cure may result in a higher potting Tg than room temp cure
> which can affect the low temp cycling performance of the potting.
> Something to
> think about if you have a choice. We pot products for harsh
> environments.
> If you are not worried about -40 or +125C you have less to worry
> about.
>
> CTE mismatch between potting/boards/components can definitely cause
> failures and fracture solder joints. Make sure you understand the
> potting properties for the temperature range, and I would run strain
> gages during temp cycling to verify. We often find some of this
> potting data you need is not included in the datasheets. Work with the
> potting manufacturer.
> Harder pottings can work, but CTE mismatch is more of a concern and
> needs to be tested to make sure it will work for your product spec.
>
> The smaller the potting volume also reduces these risks. Most issues
> we see are with larger products and not small sensors.
>
>
>
> Roger Mack P.Eng.
> Manufacturing Specialist
> Parker Hannifin Electronic Controls
> Electronic Controls Division
> 1305 Clarence Avenue
> Winnipeg, MB R3T 1T4 Canada
> direct 204 453 3339 x373
> [log in to unmask]
> www.parker.com/ecd
>
>
>
>
>
>
>
> From: Phil Bavaro <[log in to unmask]>
> To: <[log in to unmask]>
> Date: 07-08-2014 02:04 PM
> Subject: [TN] High cure temp for potting electronics
> Sent by: TechNet <[log in to unmask]>
>
>
>
> I was asked for my input on a design where the engineers want to fully
> pot some rigid flex pwbs with a thermal potting material that requires
> a cure cycle of 150C for two hours and cures to a Shore D hardness of
> 80.
>
> My immediate reaction was to voice concerns over intermetallic grain
> structure growth but thought that I should reach out to this group of
> experts before responding.
>
> We are using Sn63Pb37 solder. The PWAs are full of reflow oven
> compatible components. We normally do not expose our PWAs to any cure
> cycle temperatures over 110C.
>
> Does this elevated cure cycle lower the reliability of the solder
> joints (more brittle)?
>
> Will the extreme hardness of the material cause mechanical stress on
> the components?
>
> Any help is appreciated.
>
> Phil
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