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June 2014

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From:
GRIVON Arnaud <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, GRIVON Arnaud <[log in to unmask]>
Date:
Tue, 10 Jun 2014 15:54:28 +0200
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Grunde,

I fully understand and share your concerns that are growing in the industry given the current component packaging technologies.
I guess that setting a tight tolerance like +/-50µm for PCB feature location would be a good solution in most cases, but as mentioned earlier by Ahne, is it achievable by PCB manufacturers especially for large format/complex build-up boards?
Although not necessarily well known, please note also that at the PCBA level some criteria are given in IPC-7527 (Requirements for Solder Paste Printing) regarding the acceptable off-set between the solder paste deposits and the PCB pads for class 2 or 3 products. Quite unusual as acceptance criteria typically pertains to finished products (PCB , PCBA) not intermediate process.
Make your own calculations...
Best regards,

Arnaud Grivon
PCB/PCBA Technology Expert
Corporate Engineering/TGS
18, avenue du Maréchal Juin
Bât. C - Bureau C2-135
92366 Meudon-la-Forêt Cedex
France
Tél : (+33) (0)1 70 28 23 88
 [@@ THALES GROUP INTERNAL @@]

-----Message d'origine-----
De : TechNet [mailto:[log in to unmask]] De la part de Grunde Gjertsen
Envoyé : mardi 10 juin 2014 12:33
À : [log in to unmask]
Objet : Re: [TN] Misalignment

Hi

What's interesting from a manufacturing point of view is the error on the individual PCB, or multipanel where applicable, and for complex fine pitch components a 10inch panel really should be avoided in my opinion.
Let's say you have a panel or board of 300mm diagonally and an error of 0,15mm, align print from center of the board and the paste image will be shifted 0,075mm from the pads either end. Although not ideal this will leave 0,125mm between pads on a typical 0,5mm pitch component which will work reasonably well with a 0,1mm solder dam and a 0,05mm mask clearance.
In the past we have tried to order stencils to suit the dimensional errors in the PCB but that is not really practical.

IPC-2222 9.1.5 address feature location tolerance.

To monitor the accuracy over a production batch/batches the statistics from the solder paste printer is probably the best method if the printer has this feature

I actually have a case now where I need better accuracy due to large 0,4mm QFPs on a quite large board so I've asked the supplier to utilize the accuracy of the LDI to maximize accuracy on outer layers, as I understand most are using the LDI to maximize yield or increase capability by scaling the LDI image slightly to better match the innerlayers, when that is done feature location tolerance will definitely suffer.
My thought here is that providing the yield doesn't get unacceptable I can take away some of the 

Any input on this from someone with experience from manufacturing large boards with component pitch less than 0,5mm pitch circuits would be appreciated.

Grunde


-----Original Message-----
From: Ahne Oosterhof [mailto:[log in to unmask]]
Sent: 30. mai 2014 18:53
To: 'TechNet E-Mail Forum'; Grunde Gjertsen
Subject: RE: [TN] Misalignment

That rule of thumb does not work well anymore with today's fine pitch components. At 0.125mm (5 mil) per 250mm (10 inch) it means that across a panel, which is typically more than twice that distance, the allowable error would be greater than 0.25mm (10mil). Even for parts with 0.5mm (19.7mil) pitch you would be printing between pads and causing shorts.
If I recall correctly, IPC-2222 suggests image precision on a circuit board should be whatever the drawing states. 
Now the question is: how precise can ecb-s be manufactured and how do the manufacturer and the user verify that the board is meeting a desired/necessary spec?
This can become an issue when depaneling individual boards (how close can you route or cut to the individual board edge) and when procuring a stencil that matches the board or panel.

Ahne. 


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Grunde Gjertsen
Sent: Friday, May 23, 2014 3:44 AM
To: [log in to unmask]
Subject: Re: [TN] Misalignment

Hi

I assume you have a misalignment in solder paste printing due to pattern inaccuracy on the PCB.
Some of the newer printers can actually record and report the data, if not use the vision system in the pick and place machine to measure how much stretch you have from one corner to the other.
There is a guideline in IPC-2222 9.1.5 but how good accuracy you will need on a specific product depends on board size and lead pitch. 0,125mm per 250mm is acceptable as a rule of thumb and achievablefor the PCB supplier. LDI may or may not give better accuracy depending on how much the supplier compensates to accommodate  inaccuracies on the inner layers.

Rgds
Grunde Gjertsen

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Lyon
Sent: 23. mai 2014 12:19
To: [log in to unmask]
Subject: [TN] Misalignment

Hi all, We printed Top side of some boards with two vendors,but only one suppier found misalignment issue. what detailsFA we can do to prove the failure caused by FAb Lyon Yuan ?? Android ????

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