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June 2014

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From:
"Joel S. Peiffer" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Tue, 24 Jun 2014 11:58:05 -0500
Content-Type:
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Hi Jack,

I agree with you that many people have provided recommendations based on 
breakdown/arcing in the air or on the surface of the board and NOT through 
the dielectric.  These are completely different issues.

Although I primarily deal with much thinner dielectrics (3 um to 50 um) 
and lower voltages (<1V to 200V), I would be completely shocked and amazed 
if someone was using ~3.2 mm dielectric thickness between 1700 V for 
breakdown resistance.  As I noted earlier, when I have seen designs that 
incorporate very high voltage ( >1000V), many of them utilize polyimide 
films that have a significantly higher dielectric strength than FR-4.

If I were designing a very high voltage board using FR-4, I would not rely 
on any table from an industry guide or a rule of thumb.  There are way too 
many variables that can very significantly impact the breakdown voltage 
and electromigration.

Regards, Joel

 
Joel S. Peiffer
3M Electronic Materials Solutions Division
3M Center, Building 201-1E-17
St. Paul, MN  55144
Tel:  (651) 575-1464
Cell:  (612) 327-1983
[log in to unmask]



From:   Jack Olson <[log in to unmask]>
To:     <[log in to unmask]>
Date:   06/24/2014 09:04 AM
Subject:        Re: [TN] z-axis voltage separation
Sent by:        TechNet <[log in to unmask]>



Thank You for the reference. I didn't read it word for word, but it is 
primarily dealing with the same subject as IPC Table 6-1 (lead to lead 
clearance, or any conductive to conductive, creepage across surfaces, 
around grooves and corners, over protrusions, through air, etc.) in other 
words, CREEPAGE and CLEARANCE.

I'm asking about only one factor (layer to layer through a dielectric, 
inside a PCB layer structure, masked and conformally coated, no exposed 
anything) the answers from both TechNet and the Designer Council fall into 
two major categories:
1) those that recommend about 0.2 mm spacing
2) those that recommend about 3.2 mm spacing

Such a huge difference, and respectable opinions on both sides. This seems 
like an area that could use some work. And if anyone like an IPC committee 
takes it on, maybe we could revise Table 6-1 while we're at it. 
0.1 mm for 100V, 
0.2 mm for 101V?
seriously?
c'mon... 

thanks for supporting the fact that I'm not crazy for asking,
Jack



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