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June 2014

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From:
Robert Kondner <[log in to unmask]>
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Date:
Tue, 24 Jun 2014 10:31:35 -0400
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Jack,

 You are correct, folks keep feeding us creepage and clearance info. There are many technicians out there that will repeat what they know even if it answers a different question. We just need to wade through the noise and look for real data.

 Look for the terms "Reinforced Insulation" where they talk about minimum thicknesses but that still does not answer our questions directly. 

 Best I can tell we need to deal with "Insulation Resistance". A temperature and humidity soak followed by a resistance check at a certain voltage. 

 If I find anything I will let you know but I bet someone on this list does know, we just need to hear from them.

Bob K.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Tuesday, June 24, 2014 10:04 AM
To: [log in to unmask]
Subject: Re: [TN] z-axis voltage separation

Thank You for the reference. I didn't read it word for word, but it is primarily dealing with the same subject as IPC Table 6-1 (lead to lead clearance, or any conductive to conductive, creepage across surfaces, around grooves and corners, over protrusions, through air, etc.) in other words, CREEPAGE and CLEARANCE.

I'm asking about only one factor (layer to layer through a dielectric, inside a PCB layer structure, masked and conformally coated, no exposed anything) the answers from both TechNet and the Designer Council fall into two major categories:
1) those that recommend about 0.2 mm spacing
2) those that recommend about 3.2 mm spacing

Such a huge difference, and respectable opinions on both sides. This seems like an area that could use some work. And if anyone like an IPC committee takes it on, maybe we could revise Table 6-1 while we're at it. 
0.1 mm for 100V,
0.2 mm for 101V?
seriously?
c'mon... 

thanks for supporting the fact that I'm not crazy for asking, Jack

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