Thank You for the reference. I didn't read it word for word, but it is primarily dealing with the same subject as IPC Table 6-1 (lead to lead clearance, or any conductive to conductive, creepage across surfaces, around grooves and corners, over protrusions, through air, etc.) in other words, CREEPAGE and CLEARANCE.

I'm asking about only one factor (layer to layer through a dielectric, inside a PCB layer structure, masked and conformally coated, no exposed anything) the answers from both TechNet and the Designer Council fall into two major categories:
1) those that recommend about 0.2 mm spacing
2) those that recommend about 3.2 mm spacing

Such a huge difference, and respectable opinions on both sides. This seems like an area that could use some work. And if anyone like an IPC committee takes it on, maybe we could revise Table 6-1 while we're at it. 
0.1 mm for 100V, 
0.2 mm for 101V?
seriously?
c'mon... 

thanks for supporting the fact that I'm not crazy for asking,
Jack