Thanks, Ahne,
but I am talking about a trace above other copper layers (z-axis
clearance), and I can't make the board more than 3.25 mm thick.

It seems like most people have the impression that the IPC Table 6-1 and
the online calculators that were developed for creepage ACROSS a dielectric
should be used to predict the space required THROUGH a dielectric.

I doesn't seem sensible, but with my lack of knowledge on the subject it
would be unwise for me to argue the point.

thanks,
Jack


On Fri, Jun 20, 2014 at 9:05 PM, Ahne Oosterhof <[log in to unmask]> wrote:

> http://www.smps.us/pcbtracespacing.html
> 1700 Vdc or 1700 Vac --> use peak voltages!
> In the above website they follow formulas like you found, resulting in
> 3.25 mm. But also indicate you can use smaller distances under given
> conditions.
> Depending on the product this goes into you may have to surround the HV
> area with a moat (routed slot) to minimize the board area required for this
> circuit.
> Also, glass (in the fibers) and epoxy have different dielectric constant,
> resulting in in unequal voltage drop across parts of the ecb interior
> insulation. In turn this can lead to unexpected high flux densities, which
> in turn can lead to corona, followed by arcing.
>
> Good luck,
> Ahne.
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Jack Olson
> Sent: Friday, June 20, 2014 8:38 AM
> To: [log in to unmask]
> Subject: [TN] z-axis voltage separation
>
> maybe I'm having a "not enough coffee yet" morning, but I was asked how
> much separation I need between layers for high voltage.
> I tried to search the TechNet Archives, but it doesn't seem to work as
> well as it used to!
> anyway,
>
> We have a design that may have 1700V in several places.
> Since we are looking at a clearance into the board, layer-to-layer I'm
> pretty sure I can use the "internal" column B1 of Table 6-1 in IPC-2221
> (using Table 6-1 for z-axis was discussed in an IPC committee meeting and
> no one disagreed)
>
> but the number I get for 1700V is =
> (.25 mm for the first 500V) plus (.0025 mm for each of the other 1200V, 3
> mm)
> equals 3.25 mm
>
> For one thing, it already seems like I'm off-track because .25 for 500V
> doesn't correspond very well with 3 mm for 1200V, but if you can't trust
> IPC..... well, let's not go there.
>
> My REAL question is that, although I'm safe using 3.25 mm, my board is not
> that thick!
> Is there a smaller z-axis clearance that can be used for 1700V? across
> typical FR4 material?
> (we are using a RoHS compatible 170Tg /126)
>
> What's the MINIMUM layer spacing I can use for 1700V?
>
> thanks,
> Jack
>
>
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