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June 2014

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Subject:
From:
Wayne Thayer <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Wayne Thayer <[log in to unmask]>
Date:
Fri, 20 Jun 2014 16:54:58 +0000
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Hi Jack-

Once you are thick enough to avoid direct arcing, you have to worry about CAF, 
which is voltage stress induced.  This USUALLY causes shorts along fibers 
disturbed by the drilling, but I've seen it induced directly layer-to-layer if 
there is only one layer of weave to the dielectric.  I guess that wouldn't 
happen with the thicknesses you're talking about, but if you run 48V telecom 
buses on 75 micron dielectrics, it isn't surprising.

I've done up to 30,000V, but only single layer in the vicinity of that, with 
everything backed away to get a voltage stress under about 600V/mm surface 
flash (conformal coated).

Sounds like you need to be around the 800V/mm level within your board, and 
boards SHOULD BE less susceptible to arcing than traces on the surface 
protected only by conformal coat.

So, I'd say it's possible to build a board that way, but I'd go to 
CAF-resistant laminate material (basically gooey-er so it is less susceptible 
to resin/fiber separation) and maintain a ridiculously large via to conductor 
clearance (3-4mm sounds good).  And then, since you are outside of the generic 
specs, qualify the construction with some form of HAST.

Wayne


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Friday, June 20, 2014 11:38 AM
To: [log in to unmask]
Subject: [TN] z-axis voltage separation

maybe I'm having a "not enough coffee yet" morning, but I was asked how much 
separation I need between layers for high voltage.
I tried to search the TechNet Archives, but it doesn't seem to work as well as 
it used to!
anyway,

We have a design that may have 1700V in several places.
Since we are looking at a clearance into the board, layer-to-layer I'm pretty 
sure I can use the "internal" column B1 of Table 6-1 in IPC-2221 (using Table 
6-1 for z-axis was discussed in an IPC committee meeting and no one disagreed)

but the number I get for 1700V is =
(.25 mm for the first 500V) plus (.0025 mm for each of the other 1200V, 3
mm)
equals 3.25 mm

For one thing, it already seems like I'm off-track because .25 for 500V 
doesn't correspond very well with 3 mm for 1200V, but if you can't trust 
IPC..... well, let's not go there.

My REAL question is that, although I'm safe using 3.25 mm, my board is not 
that thick!
Is there a smaller z-axis clearance that can be used for 1700V? across typical 
FR4 material?
(we are using a RoHS compatible 170Tg /126)

What's the MINIMUM layer spacing I can use for 1700V?

thanks,
Jack


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