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March 2014

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From:
"lduso - Diamond-MT.com" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, lduso - Diamond-MT.com
Date:
Mon, 17 Mar 2014 17:37:22 -0400
Content-Type:
text/plain
Parts/Attachments:
text/plain (118 lines)
That's always been the confusing part, there needs to be a third area in
the "plain language". Coating where it *needs* to be, no coating where it
*cannot* be, and areas where coating *can* be, but doesn't *have *to be.

Coating can (and often does) de-wet on top of component or de-wets out in
the middle of the soldermask, no place that requires coating but somewhere
that is not worth masking. Is that a reject?

Lloyd Duso
Diamond-MT
Plant Manager
(814) 535-3505
www.Diamond-mt.com


On Mon, Mar 17, 2014 at 5:15 PM, Jack Crawford <[log in to unmask]> wrote:

> The plain language requirements for conformal coating are:
> Coating shall be where it is required to be, and there shall not be any
> coating where it isn't required.
>
> J-STD-001E Clause 10.1.1 Application Coating shall [D1D2D3] be applied in
> a continuous manner TO ALL AREAS DESIGNATED FOR COVERAGE ON
> THE ASSEMBLY DRAWING/DOCUMENTATION.
>
> IPC-A-610E Clause 10.8.2 Acceptable - Class 1,2,3 Coating only in those
> areas WHERE COATING IS REQUIRED. Defect - Class 1,2,3 Coating is on areas
> required to be free of coating, e.g., mating surfaces, adjustable hardware,
> wicking into connector housings, etc.
>
> If the drawings/documentation don't require coating J-STD-001 and
> IPC-A-610 don't separately cause a requirement for coating.
>
> Jack Crawford
> Certification and Assembly Technology
> IPC - Association Connecting Electronic Industries®
> 3000 Lakeside Dr. Suite 309S
> Bannockburn, IL 60015
> 847-597-2893
> Fax 847-615-5693
> [log in to unmask]
> www.ipc.org
> www.ipc.org/status  www.ipc.org/certification  www.ipc.org/downloads
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Richard Kraszewski
> Sent: Sunday, March 16, 2014 5:44 PM
> To: Technet
> Subject: Re: [TN] Confusion about conformal coating area
>
> You and your organization are not the only ones being driven crazy by this
> these specifications. Current J-Std-001 leads you to believe all must be
> coated.  The A610 seems to  make better use of the  acronym AABUS (as
> agreed between user and supplier).   In my experience, you can sometimes
> explain and convince  the customer that there is little value in coating
> the side of  molded components. Only try electrical conductors.
>
> More often than not, this is easier  done at the start of a program
>  rather than after the fact.
>
> Rich Kraszewski
> PLEXUS
> (920)969-6075
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Çetin Yegin
> Sent: Friday, March 14, 2014 3:02 AM
> To: [log in to unmask]
> Subject: [TN] Confusion about conformal coating area
>
> Dear All,
>
> We have a confusion about conformal coating area. Our quality department
> rejects some boards because edges of some high components were not coated.
> These edges are non-conductive and I think there is no need to coat
> non-conductive areas. IPC-A-610 10.5.2 says that "Conformal coatings should
> be transparent, uniform in color and consistency and uniform cover the
> board and components".
>
> 1.       Does it mean we have to coat all areas unless specified in design
> document?
>
> 2.       Is there any requirement to coat non-conductive areas?
>
> 3.       Do we have to coat non-conductive areas of components?
>
>
> Thanks.
>
> Best Regards
>
> Çetin YEĞİN
> Senior Engineer
>
> ASELSAN A.S. \ ASELSAN INC.
> Microelectronics, Guidance and Electro-Optics Division (MGEO) Çankırı
> Yolu, 7. km, 06750 AKYURT, ANKARA, TURKEY
> Phone: +90 (312) 847 53 00 Ext:4071
> Fax: +90 (312) 847 53 20
>
>
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