TECHNET Archives

March 2014

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Jason Zhao <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Jason Zhao <[log in to unmask]>
Date:
Fri, 14 Mar 2014 11:39:07 -0500
Content-Type:
text/plain
Parts/Attachments:
text/plain (145 lines)
Wow, just read the new definition and I think it will add to more confusion
and misunderstanding between board designer and fabricators. 

As a board fabricators, here is what I use,

Microvias always mean laser drilled blind vias. (they may later become
buried vias in higher density HDI, for example, 2+N+2)
PTH can be drilled by laser but I don't call them Microvias.
Blind vias can be controlled depth drilled or be created as PTH by
sub-panels, but again I don't called them microvias, usually I use
"mechanically drilled blind vias".
Via in pad is a technology, not a type of vias. It can be for PTH or blind
vias. 

But again, each fabricator use the terms differently. I think the best way
is to define vias by layer, for example, vias L1-4, vias L3-8, etc, and let
the fabricators decide what they want to do with them.

Best Regards,

Jason Zhao
VP of North America Operations
Sunshine Global PCB Group
3400 Silverstone Drive, Suite 139, Plano, TX 75023
US Cell 510-468-4412, China Cell 131-62722392
High Mix, High Tech, Low-Mid Volume PCB Manufacturer
www.sunshinepcbgroup.com
VISIT US AT IPC APEX/EXPO, Mar. 25-27th  in Las Vegas, Booth #1838




-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ragesh
Sent: Friday, March 14, 2014 6:14 AM
To: [log in to unmask]
Subject: Re: [TN] Via classification in Fabrication world

A recent blog pot in IPC website clarifies the confusion over the definition
of Microvia

http://blog.ipc.org/2014/01/10/new-microvia-definition-seeing-broader-usage/

*New Microvia Definition Seeing Broader Usage*

*In 2013, IPC changed its definition of a microvia. Before then, a microvia
was defined as any printed board with holes that have a diameter of equal to
or less than 0.15 mm [0.006 in]. Over time, that size became common, while
more challenging geometries emerged to alter the definition of microvia
structures.*

*IPC decided it was pointless to continue setting strict size parameters
that would need to be updated continually.*

*Now, microvia structures are being defined by the aspect ratio of a hole,
which is the ratio of the length or depth of a hole to its preplated
diameter. This approach acknowledges that a hole diameter of, say 0.10 mm
[0.004 in] will be challenging to adequately plate with copper on a 10-layer
board (high aspect ratio), while the same size hole will be comparatively
easy to plate if the board has two layers (low aspect ratio) that use the
same materials in the 10-layer board.*

*This definition has until recently been found only in IPC-T-50K, Terms and
Definitions for Interconnecting and Packaging Electronic Circuits, published
in June 2013. The new definition is now being phased into printed board
design and performance standards. IPC-6013C, Qualification and Performance
Specification for Flexible Printed Boards, published in December 2013, is
the first to cite this definition.*

*This year, additional standards and handbooks will migrate to the revision.
That will make life simpler for companies that want to differentiate
microvia capabilities and requirements as technology continues to evolve.*

Again its best to talk to your fab house to make sure if they align to the
same or not.

-Ragesh.


On 14 March 2014 15:09, Nagaraj Shanmugam <
[log in to unmask]> wrote:

> Experts,
>
> I ran into misunderstanding often on via classification on PCBs  and 
> like to have clear understanding on this forum.
> As layout designer I classify vias
>         - based on drill depth as Blind via(external to internal), 
> Buried via(with in internal) and through hole via (external to external).
>         - based on via stack as Stacked via(Blind/Buried vias placed 
> at same locations) and staggered via (blind/buried via placed apart 
> may have pad overlaps)
>
> I am fine and clear up to hear.
>
> Now, as I discuss with latest technologies /package
>         - on tighter pitch BGAs say 0.4mm pitch BGA's the VIP(via in 
> pad) come into role and need via filling.
>         - high power ICs with thermal pad which needs thermal vias for 
> heat dissipation, these via need plugging
>
> Here the discussion starts with Fabricator's and lead to 
> misunderstanding on via definitions
> - They call  Microvia to plate and shut copper
>         What micro via means?
>                 a) Some refers to  Blind via but with limitation in 
> the depth that the can only go one layer down from external layers 
> with drill size less than 6mils.
>                 b) some inform they are Via in Pad using blind vias 
> which is of drill size 6mils and less
>                 c) some refers to any via of drill size less than 
> 6mils and is laser drilled called Microvia and the via doesn't matter 
> blind/buried/through hole
>                 d) few other says its HDI(- High density interconnect) 
> via and this includes Blind and buried but not through hole via
>
> I am totally lost here - Please help to understand the via 
> terminologies in Fabrication world specifically Microvia.
>
> Thanks in advance for your inputs.
>
> Thanks,
> Nagaraj.
>
>
> ______________________________________________________________________
> This email has been scanned by the Symantec Email Security.cloud service.
> For more information please contact helpdesk at x2960 or 
> [log in to unmask] 
> ______________________________________________________________________
>


______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or [log in to unmask]
______________________________________________________________________



______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or [log in to unmask] 
______________________________________________________________________

ATOM RSS1 RSS2