I'm not disputing anything Marc said, but in my opinion Table 6-1 is one of
the weakest in the IPC "foundation".
If you ever hear Dieter tell the story of how the table came to be, you'll
wonder what the final numbers mean
(except for the empirical evidence that people have been using them for
decades with no serious consequences)

but even using your own common sense, look at column 1 (or B1):
100 volts needs 4 mils clearance, but 101 volts needs 8 mils?
absurd.

Regardless, I doubt the originators of the table ever intended those
numbers to mean the spacing in the vertical direction,
since that separation would be real insulating material with minimum
thickness requirement,
What was needed was a guideline for conductors in the same plane (edge to
edge spacing),
with variable air, solder mask material or conformal coating between.

So I know I'm not helping you Larry, but I wonder if scientific data would
show that
clearance ACROSS a material should be different than THROUGH a material.

just my opinion, but Table 6-1 needs to be revisited.

Jack


On Mon, Mar 10, 2014 at 3:06 PM, Anne Marie Mulvihill <
[log in to unmask]> wrote:

> IPC Director of Technology Transfer, Marc Carter, weighs in...
> Subject: RE: [DC] IPC-2221B Electrical Spacing
>
> Yes, the raw material in perfect, undisturbed, pristine state, in a
> laboratory, has a theoretical maximum isolation of 300v per mil. No
> drilling. No irregular "tooth" on the back of the copper. No lamination
> effects, no chemical immersion, no nothing that would disturb it's perfect,
> theoretical maximum.
>
>    Class 3 is predicated on GUARANTEED stability and long-term reliability
> as the goal. As such it will be VERY conservative.
> One POSSIBLE alternative would be to build to Class 3 with the exception
> of the isolation, and test it under various environmental stressors for
> whatever the customer and this builder agreed is sufficient time to develop
> any latent defects.
>
> Another POSSIBLE alternative is that it's possible that 500 v isolation is
> not required between EVERY layer of the board. Symmetry is great, but if
> you HAVE to build an assymetric stack up, and you can deal with the
> degradation in warp and twist that may bring, then that's an avenue. I've
> done it. Don't care to, but sometimes, ya gotta.
>
>   If you want it to meet the implications of Class 3, then you kinda have
> to build it to Class 3 (production allowances, exposures, chemistry, etc.)
> and all.
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Larry
> Brophy
> Sent: Monday, March 10, 2014 2:26 PM
> To: DesignerCouncil
> Subject: [DC] IPC-2221B Electrical Spacing
>
> Hi all, is there any table besides Table 6-1 in IPC-2221B that I can use
> for the layer seperation that takes into account the voltage resistance of
> FR4.  I know FR4 is good for 300V per mil and I need 500V isolation, if I
> use Table 6.1 I'm going to need  9.74mil between layers and have a very
> thick board.
>
> I have a customer that wants the design to be Class 3 and insists that I
> use this table unless I can find something in an IPC spec that allows me to
> use the voltage resistance of FR4 instead of this table.
>
> Many thanks,
>
> Larry
>
>
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