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March 2014

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Subject:
From:
"Brooks, William" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Mon, 10 Mar 2014 16:58:58 -0400
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Okay... I'm sorry but this isn't very funny... 
This forum uses ascii text messages only... whatever text editor you are using is not using plain text. 
Please reconfigure your mail editor to use plain text for this forum. 
Thank you kindly... :)

To comment on the topic... 

The interpretations I have seen here of the spec assume a lot...  This voltage requirement came from the military PCB material specs... MIL-P-13949 if I remember correctly. Also The old  "0.0002 in./volt" (0.00508 mm/volt) reference in there originally came from MIL-I-46058.

The issue with voltage spacings being different across the surface of a board rather than thru it can be explained simply. 
The surfaces of the layers are exposed to chemical processing 'dirt' or other contaminants... the inner core materials are basically cross sectionally homogenous and are less likely to have imperfections or ionic paths... or other ways for arcing to occur thru the material... It's much more likely that a voltage will 'leak' or find a lower resistance path across the surface of the pcb material than it will thru it. 

The number I recall is 700VDC per mil thru the material max. (that means zero margin or tolerance). 
The IPC chart was for spacing across the surface outside and inside the board for multilayer boards... 
Is that how you see it?


William Brooks, CID+
Senior MTS (Contract) 
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax:        760.918.8332
Mobile:    760.216.0170
E-mail:    [log in to unmask]




-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Monday, March 10, 2014 1:37 PM
To: [log in to unmask]
Subject: Re: [DC] FW: [DC] IPC-2221B Electrical Spacing


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