We have been using the following note to specify minimum dielectric spacing in a Class 2 MIL environment and it should meet the requirements of Class 3 as well.
" THE MINIMUM DIELECTRIC THICKNESS SHALL BE 0.005” WITH A MINIMUM OF 2 LAYERS OF GLASS BETWEEN ALL CONDUCTIVE LAYERS, OR SHALL MEET THE HIGH POT TESTING REQUIREMENTS TO WITH STAND *** VOLTS FOR 30 SECONDS. SEE THE STACK-UP DIAGRAM FOR NOMINAL DIMENSIONS AND TOLERANCES."
The voltage requirement is design dependant with a 500, 1k, 2.5k, 5k, 10k, 25k test levels.
This was derived from the old MIL-STD-275 design requirements and MIL- S-13949 materials documents.
Jeffrey McGlaughlin, C.I.D.
Engineering Designer
Battelle
505 King Avenue
Columbus Ohio 43201-2693
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-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Larry Brophy
Sent: Monday, March 10, 2014 3:26 PM
To: [log in to unmask]
Subject: [DC] IPC-2221B Electrical Spacing
Hi all, is there any table besides Table 6-1 in IPC-2221B that I can use for the layer seperation that takes into account the voltage resistance of FR4. I know FR4 is good for 300V per mil and I need 500V isolation, if I use Table 6.1 I'm going to need 9.74mil between layers and have a very thick board.
I have a customer that wants the design to be Class 3 and insists that I use this table unless I can find something in an IPC spec that allows me to use the voltage resistance of FR4 instead of this table.
Many thanks,
Larry
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