Hello Phil,

I will chime in a little on this topic because I truly believe component 
cleanliness is an area that needs some exploration.  I as the vice-chair of 
IPC's Ionic Conductivity task group have been pushing for a method 
specifically dealing with components.  I will say that we are in the process 
of addressing this issue.  What I can't say is what the acceptable limits 
for components might be.  This is an area with little information available. 
However, the only specification that I am aware of regarding component 
cleanliness testing tied to solder dipping of components leads is the 
GEIA-STD-006.  The version I have has criteria defined based on the ROSE 
test methodology and virtually the same pass/fail criteria as defined in 
J-STD-001 for assemblies.  Now, I am not involved with the GEIA group effort 
and I don't know if a newer version exists with better criteria.  However, 
IMHO the criteria that the GEIA document defines is meaningless, especially 
if you are using a "no clean" flux.

Best regards,

Joe Russeau





----- Original Message ----- 
From: "Phil Bavaro" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 18, 2014 11:30 AM
Subject: [TN] Cleanliness testing at component level


>I have reviewed the J-STD-001 several times but still have a question 
>regarding a subcontractor who performs component level soldering operations 
>for Class 3 hardware.
>
>
> If the subcontractor is performing a soldering operation, then cleaning is 
> required to remove flux residues (this is not  a no clean flux situation).
>
> If the subcontractor is cleaning, then cleanliness testing is required.
>
> The J-STD-001 does not really address the component level when it comes to 
> the Post Soldering Cleanliness Designator (PSCD).
>
> If a component is having its leads pre-tinned or a BGA being re-balled, 
> then is it defaulted to a C-22 PSCD?
>
> My position is yes but I can see where there might be arguments against 
> this since the designator codes seem to speak to the assembly level and 
> not the component level.
>
> My concern is that there is considerable time lag between when component 
> soldering operations are performed relative to the actual PWA process 
> which does get checked for cleanliness.
>
> Any input is appreciated.
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