Thanks for the comment Jack... :)
This a note I have used on my drawings in the past...
BOW AND TWIST SHALL NOT EXCEED 0.75% (.0075 IN PER IN) IN ACCORDANCE WITH IPC-A-600F FOR SURFACE MOUNTED BOARDS WHEN MEASURED USING IPC-TM-650, METHOD 2.4.22.
Or...
BOW AND TWIST SHALL NOT EXCEED 1.5% (.0150 IN PER IN) IN ACCORDANCE WITH IPC-A-600F FOR THROUGH HOLE BOARDS WHEN MEASURED USING IPC-TM-650, METHOD 2.4.22.
The company I work at now has used this note traditionally
WARP OR TWIST OF BOARD SHALL NOT EXCEED 0.010" PER INCH
I'm of the opinion that a note should be unambiguous ... and clearly stated so that it cannot be misinterpreted... What have you seen?
The one thing that I see happen in industry a lot is inexperienced designers or others who layout boards making asymmetrical stackups and then wondering why they have a potato chip board when it comes back...
Typically, a good board shop will stop the job and call the designer when they see something like this in CAM.
Also I have seen boards warp after the reflow or wave soldering process... and with RoHS lead free solders the temps are even higher than we had in the past with good old SN63 tin/lead solder...
I'm particularly interested in methods to prevent warping... whether thru design or manufacture or assembly... stop it before it becomes a problem... by design.
:)
William Brooks, CID+
Senior MTS (Contract)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
From: Jack Olson [mailto:[log in to unmask]]
Sent: Thursday, February 06, 2014 7:53 AM
To: (Designers Council Forum); Brooks, William
Subject: Re: [DC] PCB Bow and Twist controls
just a "light discussion", huh? (smile)
I'm not up to speed on the latest bare board fabrication processes,
and I can't directly answer the questions at the end of your post,
but I can offer a few comments:
a) that's a pretty good list of factors you have collected, I can't think of any others
b) I think the problem is harder to control for lower layer count. Once you have a lot of copper layers, you are probably not going to see warping unless something was done drastically wrong at the fabricator
c) Its fairly easy to compensate for copper balance, either the designer can add copper fills in empty areas (if worried about affecting performance, make a larger clearance like 100 mils or something, so it really just fills the EMPTY areas) or by allowing the fabricator to add thieving to the artwork
d) It is fairly difficult to compensate for asymmetrical layer stack, unless it is a higher layer count
e) I disagree with the item 4) you listed. I think some bare board fabs have tried to do that to pass incoming inspection, and then they warp at assembly thermal. I'm pretty sure that is a bad practice!
f) I haven't heard of rails or tabs needing any particular kind of attention related to warping as you suggest in item 7)
g) I don't think long narrow boards are necessarily more prone to warping, but remember the spec allows a certain amount of warping per inch, so it may appear to be more warped than other boards and still be acceptable (I think its .7%, or 7 mils per inch? can't remember) anyway, you may be able to see an obvious warp on a long board, that is still okay, is all I was trying to say
h) yes, I know for sure that fabricators alternate the direction of the weave for adjacent layers, and if they make a mistake you can have a problem, but I should let a fabricator answer that one...
hope that helps a little bit, sorry I can't answer your questions, Mr. Bill
Jack
On Wed, Feb 5, 2014 at 2:57 PM, Brooks, William <[log in to unmask]<mailto:[log in to unmask]>> wrote:
I would like to open a light discussion on the control of bow and twist in FR4 PCB's...
I'm aware that there are many factors that can contribute to printed board warping...
Some are design related and some are fabrication material and process related
These are some design related warp inducing features...
1) Asymmetrical stack up
2) Uneven distribution of copper
3) Very long and narrow boards...
Some other suggestions I have heard of:(though not verified)
1) Copper fill or thieving on layers to distribute copper plating more evenly
2) Alternating the grain of the board layer materials to compensate for grain induced warpage
3) Reduce the resin content increase the glass fiber diameter to reinforce the strength and rigidity of the board
4) Flatten boards under heat and pressure to compensate for warp
5) Reduce lamination cycles by changing the design construction
6) Controlled cooling of boards after lamination to reduce stress
7) Pay attention to the geometry of breakaway tabs and support rails... add copper thieving to them so that they don't warp the board
My questions...
1) What if any hard research has been done in this area and have there been any white papers published that I can access?
2) How do bare board manufacturers compensate for the tendency of certain boards to warp?
3) How much does the type of material and raw material manufacturer play into the equation?
4) What recommendations do you have to avoid the issue up front in your pcb designs?
Are there others suggestions?
Are there any great published articles out there that examine the subject?
I look forward to your comments...
Thanks,
William Brooks, CID+
Senior MTS (Contract)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]<mailto:[log in to unmask]>
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