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January 2014

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Subject:
From:
"Stadem, Richard D." <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Stadem, Richard D.
Date:
Mon, 6 Jan 2014 17:09:03 +0000
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Frank,
If none of the solder on the PWB pad actually touches the bottom of the component, yet there is a dome of solder on the PWB pad, the X-ray will probably see a perfect opaque solder joint with no voiding whatsoever and calculate no voiding. What the X-ray does NOT know is that there is no connection between the bottom of the part and the pad on the board. Anytime you have solder wetting to both the pad on the board and the pad on the bottom of the part, there will be at least some voiding (typically).

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Frank Kriesch
Sent: Monday, January 06, 2014 10:48 AM
To: [log in to unmask]
Subject: [TN] Antwort: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs

Happy new year!

A little bit late, but here are my thoughts.
As been said before, the wetted area is relevant for the conduction of heat. At the beginning we tried to define the max. amount of voiding. But we saw that we have to calculate the required wetting area specific for each component.
Another question  is, what is the baseline for calculating the percentage of voids. Is it boardpad area or is it the thermalpad area of the component? The allowed tolerances for the thermalpad is huge for a calculationbaseline. Not all thermalpadarea can be wetted because of castingresidues. So what is the calculationbaseline? For some X-Ray-Machines it is easy to calculate the dark (wetted) area.

Kind regards

Frank



Von:    "Stadem, Richard D." <[log in to unmask]>
An:     <[log in to unmask]>
Datum:  23.12.2013 16:32
Betreff:        Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Gesendet von:   TechNet <[log in to unmask]>



The amount of voiding in this type of part has to be directed as a percentage of the possible overall wetting. 
Some EMS assemblers purposely reduce the amount of solder volume to ensure the periphery leads fully wet (no pendulum effect) and to avoid solder balls under the part, which is a common problem with QFNs. So, if you only have wetting over 50% of the belly pad, you may need to have a reduced amount of voiding to correspond to protect the reliability of the solder connection and the thermal transfer or current carrying capacity. 
Instead of looking at the amount of voiding, it may be better to have a general requirement for the minimum amount of wetting. Now, having said that, how do you propose to ensure that the minimum amount of wetting is actually accomplished?
Are the non-voided areas you see in the X-ray really wetted both to the bottom of the component and the top of the board pad? You cannot assume that. How do you know? Not even laminar X-ray (5DX or similar) can prove full surface-to-surface wetting beyond the "shadow of a doubt". All you see are shadows. 

Check this out:  http://www.youtube.com/watch?v=owbgPVOQlbY


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Reuven Rokah
Sent: Friday, December 20, 2013 10:18 AM
To: [log in to unmask]
Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs

Hi All,
I started with this issue because of my customer needs (max 25% voids) and argue with the EMS (one one the biggest) that its guide lines require 40% maximum of voids.
In my opinion it should be included in the IPC-A-610 such as class 1, 2, 3 and above class 3 such as 10% voids (using vapor phase), should be agreed between the two sides.


On Fri, Dec 20, 2013 at 3:04 PM, David D. Hillman < [log in to unmask]> wrote:

> Hi Joyce - sometimes we can get too technical and over think a
component.
> As you detailed, there can be a number of inputs to the equation but 
> not necessarily. We have been using the 50% maximum void rule for 5 
> years on QFNs  and I have only 2 cases where we had either a thermal 
> or grounding issue that required us to maintain a smaller voiding 
> percentage of the thermal pad.
>
> Dave
>
>
>
> From:   Joyce Koo <[log in to unmask]>
> To:     'TechNet E-Mail Forum' <[log in to unmask]>,
> "[log in to unmask]" <[log in to unmask]>
> Date:   12/20/2013 06:45 AM
> Subject:        RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of 
QFNs
>
>
>
> Correct me if I am wrong, as for the thermal goes, there are many 
> factors just the voiding.  For example, the requirements of heat 
> transfer path - vertical vs side, MCM possibly will have multiple 
> grounds that may required isolation of heat path.  If you allow 50% 
> voids, depend upon the thermal via path, you might missing one sector 
> of the MCM heat conduction path all together (if it is vertically 
> channeled).  It is not as easy as a single number.  It is a bit of 
> scary when the design is so far above the supply chain.
>
> Joyce Koo
> Researcher
> Materials Interconnect Lab
> Office: (519) 888-7465 79945
> BlackBerry: (226) 220-4760
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of David D. Hillman
> Sent: Friday, December 20, 2013 7:36 AM
> To: [log in to unmask]
> Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
>
> Hi Reuven - I think that is a possible idea, however, what void 
> percentage
>
> do you suggest and what technical data/investigative studies do you 
> have to support the recommended void percentage? One thing to consider 
> is that if a workmanship topic is missing from the JSTD-001/IPC-610 
> documents, it doesn't mean that the topic hasn't been reviewed.  The 
> IPC committees work
>
>  hard to only put workmanship criteria in the specifications that is 
> necessary and is supported by data. An example - the IPC-7093 BTC 
> committee completed extensive efforts looking at the voiding of QFN 
> thermal pads and found no industry consensus on a void percentage 
> requirement. The JSTD-001 committee therefore has not included a 
> maximum void percentage requirement in the 001 specification and the
> IPC-610 specification shows no examples of voiding requirements of QFN 
> thermal pads. The workmanship criteria show in the JSTD-001/IPC-610 
> specifications
>
> results in added costs to products and processes so the committees are 
> very careful to not add requirements unless there is technical 
> data/justification. I know a number of OEMs/CEMS who have a 50% 
> maximum void requirement on the QFN thermal pad unless the component 
> has specific thermal or electrical functional requirements. The
> IPC-7093 specification has some good information on the topic of BTC 
> thermal pads and voids. The committees would welcome any investigative 
> data on the topic too.  Happy Holidays!
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
> From:   Reuven Rokah <[log in to unmask]>
> To:     <[log in to unmask]>
> Date:   12/20/2013 12:48 AM
> Subject:        [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
> Sent by:        TechNet <[log in to unmask]>
>
>
>
> Hi TechNets,
>
> I didn't see in the IPC-A-610E any acceptability reference in regards 
> with the percentage of voids in solder joints of exposed thermal pads 
> of QFNs or other components with exposed thermal pads.
>
> I recommend to add it in the next revision.
>
>
> --
>
> Best Regards,
>
> *Reuven Rokah*
>
> Mobile: 972-52-6012018
> Tel:        972-3-9360688
> Fax:          076-5100674
>  <http://www.rokah-technologies.com/>[log in to unmask]
> [log in to unmask]
> www.rokah-technologies.com
>
>
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-- 

Best Regards,

*Reuven Rokah*

Mobile: 972-52-6012018
Tel:        972-3-9360688
Fax:          076-5100674
 <http://www.rokah-technologies.com/>[log in to unmask]
[log in to unmask]
www.rokah-technologies.com


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