Hi Dave,
Advocating might be too strong a word. Living with is probably more appropriate. I think my wife and grandchildren would like, even thought he don't understand electronic technology, it if everyone would go back to SnPb solder, through-hole and gull wing lead attachment and that way there wouldn't be much need for failure analysis and reliability engineering and I'd have more time to spend with them.
I know the QFN voiding topic isn't something Santa is going to resolve when he comes tonight and it will still be with us come the New Year.
Wishing you and all those on TN a Merry Christmas and Happy New Year!
Regards,
George
George M. Wenger
Failure Signature & Characterization Lab LLC
609 Cokesbury Road, High Bridge, NJ 08829
(908) 638-8771 Home (732) 309-8964 Mobile
E-mail: [log in to unmask]
[log in to unmask]<mailto:[log in to unmask]>
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, December 24, 2013 11:59 AM
To: Wenger, George M. [Contractor]
Cc: TechNet E-Mail Forum
Subject: RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Hi George - so you are advocating "QFN insanity in small doses?"?
Dave
From: "Wenger, George M. [Contractor]" <[log in to unmask]<mailto:[log in to unmask]>>
To: TechNet E-Mail Forum <[log in to unmask]<mailto:[log in to unmask]>>, "[log in to unmask]<mailto:[log in to unmask]>" <[log in to unmask]<mailto:[log in to unmask]>>
Date: 12/24/2013 10:41 AM
Subject: RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
________________________________
It looks like I'm in the middle between Dave and Richard. I agree with Richard's statement if you put a qualifier at the end of the statement (i.e., "QFNs should not be used in hi-reliability devices" if you have an alternative). And I agree with Dave that QFNs are very reliable components when you add several qualifiers at the end of his statement as he indicates (i.e., you need to understand the component technology, qualify and monitor your assembly process).
If I were a component vendor I'd like everyone to use QFNs because it gives me advantages. If I were solder process assembly engineer I'd rather have a component package that didn't require as much of my time as QFNs do. However, we need to be pragmatic and realize that QFNs are here and aren't going away and their use is increasing and we need live with them.
Regards,
George
George M. Wenger
Failure Signature & Characterization Lab LLC
609 Cokesbury Road, High Bridge, NJ 08829
(908) 638-8771 Home (732) 309-8964 Mobile
E-mail: [log in to unmask]<mailto:[log in to unmask]>
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David D. Hillman
Sent: Tuesday, December 24, 2013 11:06 AM
To: [log in to unmask]<mailto:[log in to unmask]>
Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Hi Richard - you and I are on the same page except for the "QFNs should not be used in hi-reliability devices". Are QFNs a complex technology to understand? Absolutely, but if you do your homework and put into place the correct process controls, QFNs are very reliable components (the IPC-7093 standard is a good starting point). The NASA DoD consortia study demonstrated that QFNs were a very reliable component technology under high performance equipment test conditions. The voiding associated with QFNs should be handled no differently than the voiding associated with BGAs - we need to understand why the voids are present, what possible impact the voids could have on the QFN component, and what steps need to be taken to have a process that produces an acceptable level of voiding (which can be wide range of acceptability). I think the point of the entire QFN/void thread has been that QFNs need to be understood as a component technology or just don't put them on your assembly.
Happy Holidays!
Dave
From: "Stadem, Richard D." <[log in to unmask]<mailto:[log in to unmask]>>
To: <[log in to unmask]<mailto:[log in to unmask]>>
Date: 12/23/2013 04:48 PM
Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Sent by: TechNet <[log in to unmask]<mailto:[log in to unmask]>>
Nobody has responded to the fact that you cannot validate you actually have surface-to-surface wetting in the non-voided areas of QFNs and other SMT components with belly pads. The point I am trying to make is that QFNs really should not be used in hi-reliability devices. I know they are, but they present so many issues, and chief amongst them is cases like Reuven's, where a total amount of voiding of 25% maximum is required by his customer.
There is no way to validate compliance to that requirement.
The entire surface of the board pad could be covered with solder with no voiding visible in the X-ray, but none of the solder may actually be wetted to the bottom of the part. I have seen this happen many times; I was called in to determine what the reliability issue was with some QFNs overheating, and others not, and the client was puzzled because the ones that failed did not show any evidence of voids, they were completely opaque. They did not show any evidence of voiding because there was little or no wetting to the bottom of the QFN, only to the board pad, therefore no heat-sinking whatsoever.
Voids only appear on belly pad solder joint X-rays if at least some of the solder is wetted to both the bottom of the part and to the pad on the PWB.
From this experience, if I see a QFN belly pad solder joint without any voids at all, I immediately suspect there is no solder contact whatsoever, not the opposite. To me, voiding manifest in the X-rays of QFN solder joints is a good thing, as it indicates solder wetting took place on both surfaces.
Now, if components fail because the amount of voiding is greater than 25% and you cannot guarantee your process will always provide less than 25% voiding, that is a design issue, not a process capability issue. Design engineers should take note of that.
I would bill extra for the rework that is going to happen to meet that particular requirement.
From: Reuven Rokah [mailto:[log in to unmask]]
Sent: Monday, December 23, 2013 10:04 AM
To: Stadem, Richard D.
Cc: TechNet E-Mail Forum
Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Hi Richard,
If you design the thermal pad by dividing its area to small thermal pads you will improve the air escape possibility during the soldering process, reduce the voids creation and increase wetting.
Same you have to design the stencil and its thickness accordingly.
Still I am recommending to add requirements for the Power QFN voids.
On Mon, Dec 23, 2013 at 5:30 PM, Stadem, Richard D.
<[log in to unmask]<mailto:[log in to unmask]>> wrote:
The amount of voiding in this type of part has to be directed as a percentage of the possible overall wetting.
Some EMS assemblers purposely reduce the amount of solder volume to ensure the periphery leads fully wet (no pendulum effect) and to avoid solder balls under the part, which is a common problem with QFNs. So, if you only have wetting over 50% of the belly pad, you may need to have a reduced amount of voiding to correspond to protect the reliability of the solder connection and the thermal transfer or current carrying capacity.
Instead of looking at the amount of voiding, it may be better to have a general requirement for the minimum amount of wetting. Now, having said that, how do you propose to ensure that the minimum amount of wetting is actually accomplished?
Are the non-voided areas you see in the X-ray really wetted both to the bottom of the component and the top of the board pad? You cannot assume that. How do you know? Not even laminar X-ray (5DX or similar) can prove full surface-to-surface wetting beyond the "shadow of a doubt". All you see are shadows.
Check this out: http://www.youtube.com/watch?v=owbgPVOQlbY
-----Original Message-----
From: TechNet [mailto:[log in to unmask]<mailto:[log in to unmask]>] On Behalf Of Reuven Rokah
Sent: Friday, December 20, 2013 10:18 AM
To: [log in to unmask]<mailto:[log in to unmask]>
Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Hi All,
I started with this issue because of my customer needs (max 25% voids) and argue with the EMS (one one the biggest) that its guide lines require 40% maximum of voids.
In my opinion it should be included in the IPC-A-610 such as class 1, 2, 3 and above class 3 such as 10% voids (using vapor phase), should be agreed between the two sides.
On Fri, Dec 20, 2013 at 3:04 PM, David D. Hillman < [log in to unmask]<mailto:[log in to unmask]>> wrote:
> Hi Joyce - sometimes we can get too technical and over think a
component.
> As you detailed, there can be a number of inputs to the equation but
> not necessarily. We have been using the 50% maximum void rule for 5
> years on QFNs and I have only 2 cases where we had either a thermal
> or grounding issue that required us to maintain a smaller voiding
> percentage of the thermal pad.
>
> Dave
>
>
>
> From: Joyce Koo <[log in to unmask]<mailto:[log in to unmask]>>
> To: 'TechNet E-Mail Forum' <[log in to unmask]<mailto:[log in to unmask]
>>,
> "[log in to unmask]<mailto:[log in to unmask]>'"
<[log in to unmask]<mailto:[log in to unmask]>>
> Date: 12/20/2013 06:45 AM
> Subject: RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of
QFNs
>
>
>
> Correct me if I am wrong, as for the thermal goes, there are many
> factors just the voiding. For example, the requirements of heat
> transfer path - vertical vs side, MCM possibly will have multiple
> grounds that may required isolation of heat path. If you allow 50%
> voids, depend upon the thermal via path, you might missing one sector
> of the MCM heat conduction path all together (if it is vertically
> channeled). It is not as easy as a single number. It is a bit of
> scary when the design is so far above the supply chain.
>
> Joyce Koo
> Researcher
> Materials Interconnect Lab
> Office: (519) 888-7465 79945
> BlackBerry: (226) 220-4760
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]<mailto:[log in to unmask]>] On
> Behalf
Of David D. Hillman
> Sent: Friday, December 20, 2013 7:36 AM
> To: [log in to unmask]<mailto:[log in to unmask]>
> Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
>
> Hi Reuven - I think that is a possible idea, however, what void
> percentage
>
> do you suggest and what technical data/investigative studies do you
> have to support the recommended void percentage? One thing to consider
> is that if a workmanship topic is missing from the JSTD-001/IPC-610
> documents, it doesn't mean that the topic hasn't been reviewed. The
> IPC committees work
>
> hard to only put workmanship criteria in the specifications that is
> necessary and is supported by data. An example - the IPC-7093 BTC
> committee completed extensive efforts looking at the voiding of QFN
> thermal pads and found no industry consensus on a void percentage
> requirement. The JSTD-001 committee therefore has not included a
> maximum void percentage requirement in the 001 specification and the
> IPC-610 specification shows no examples of voiding requirements of QFN
> thermal pads. The workmanship criteria show in the JSTD-001/IPC-610
> specifications
>
> results in added costs to products and processes so the committees are
> very careful to not add requirements unless there is technical
> data/justification. I know a number of OEMs/CEMS who have a 50%
> maximum void requirement on the QFN thermal pad unless the component
> has specific thermal or electrical functional requirements. The
> IPC-7093 specification has some good information on the topic of BTC
> thermal pads and voids. The committees would welcome any investigative
> data on the topic too. Happy Holidays!
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]<mailto:[log in to unmask]>
>
>
>
> From: Reuven Rokah <[log in to unmask]<
mailto:[log in to unmask]>>
> To: <[log in to unmask]<mailto:[log in to unmask]>>
> Date: 12/20/2013 12:48 AM
> Subject: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
> Sent by: TechNet <[log in to unmask]<mailto:[log in to unmask]>>
>
>
>
> Hi TechNets,
>
> I didn't see in the IPC-A-610E any acceptability reference in regards
> with the percentage of voids in solder joints of exposed thermal pads
> of QFNs or other components with exposed thermal pads.
>
> I recommend to add it in the next revision.
>
>
> --
>
> Best Regards,
>
> *Reuven Rokah*
>
> Mobile: 972-52-6012018
> Tel: 972-3-9360688
> Fax: 076-5100674
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