Yap. Good memory ;-).
Product that are built around function alone have not been designed at all, but merely engineered. -prof. Ashby
Original Message
From: Bev Christian
Sent: Friday, December 20, 2013 6:34 PM
To: 'TechNet E-Mail Forum'; 'Reuven Rokah'; Joyce Koo
Subject: RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
I don't have our company standard in front of me, which I helped write - but
can't remember the particulars right now. Old age?
Anyways OUR designers wanted a max of FIFTEEN % voids under PA QFNs. We
wanted to tell them where to go, but decided just to whisper at the walls.
That being said, we knew getting there would be really, really tough in some
instances. We made a distinction between power QFNs and others and where
the voids sat in reference to the actual silicon chip.
Joyce,
Did I get that last bit right?
Bev
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Reuven Rokah
Sent: Friday, December 20, 2013 3:23 PM
To: [log in to unmask]
Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Thanks Dave,
I hope the committee will consider it in the next revision.
On Fri, Dec 20, 2013 at 10:03 PM, <[log in to unmask]> wrote:
> Hi Reuven - while I whole heartedly agree that it would be much easier to
> do, how are we going to list a component specific function in the
JSTD-001?
> That list of components would be a mile long and ten feet deep. The
> JSTD-001/IPC-610 contain requirements and criteria that are applicable to
> classes or groups of component technologies. The 40% maximum void criteria
> does not apply to all QFN style components so its inclusion would benefit
> some users but not all users which is a condition that the committee
> avoids. It would be great if the JSTD-001/IPC-610 specifications would
take
> care of all of the component issues but there are some
> requirements/criteria which are design/component specific which are what
> drawing notes are intended for.
>
> Dave
>
>
>
> From: Reuven Rokah <[log in to unmask]>
> To: [log in to unmask]
> Cc: TechNet E-Mail Forum <[log in to unmask]>
> Date: 12/20/2013 01:51 PM
> Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
> ------------------------------
>
>
>
> Agree,
> It will be easier to define in the SOW (Statement of Work) the required
> percentages in accordance with IPC class 1,2 or 3.
>
>
> On Fri, Dec 20, 2013 at 9:37 PM,
<*[log in to unmask]*<[log in to unmask]>>
> wrote:
> HI Reuven - If the QFN component has specific thermal dissipation or
> electrical grounding requirements, then the customer is leveling the 25%
> maximum void requirement for a data driven reason which is how we want
such
> requirements to be determined. Not all QFN or BTC components have those
> specific physical requirements.
>
> Dave
>
>
>
> From: Reuven Rokah
<*[log in to unmask]*<[log in to unmask]>
> >
> To: *[log in to unmask]* <[log in to unmask]>
> Cc: TechNet E-Mail Forum <*[log in to unmask]* <[log in to unmask]>>
> Date: 12/20/2013 12:35 PM
> Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
> ------------------------------
>
>
>
> Hi Dave,
> Its high power QFN and there are 8 QFNs on each PCBA.
> Heat sink is connected to the bottom side of the PCB. 40%-50% voids will
> not transfer the heat generated correctly.
>
>
> On Fri, Dec 20, 2013 at 6:38 PM,
<*[log in to unmask]*<[log in to unmask]>>
> wrote:
> Hi Reuven - I would ask the customer where/how they arrived at the 25% max
> void value as it sure sounds to me like they are using the current BGA 25%
> max void criteria. I have to routinely explain to some of our customer
base
> that just because the JSTD-001 specification doesn't contain a specific
> requirement, such as voids on a QFN thermal pad, it doesn't mean they
> forgot to include it the document. If fact, the opposite is very much
true,
> the lack of a requirement or criteria for a specific topic item is
> typically proof that there is no industry consensus on what the
requirement
> should be or that a requirement is not necessary. Now if a customer has
> established a QFN voiding requirement, then you need to directly work with
> them to discuss why they feel the requirement is necessary - and note
that
> workmanship requirements drive product costs through process controls,
> inspection protocols and documentation. No free lunch (unless I can get
> Doug to buy).
>
> Dave
>
>
>
> From: Reuven Rokah
<*[log in to unmask]*<[log in to unmask]>
> >
> To: TechNet E-Mail Forum <*[log in to unmask]* <[log in to unmask]>>,
> *[log in to unmask]* <[log in to unmask]>
> Date: 12/20/2013 10:18 AM
> Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
> ------------------------------
>
>
>
>
> Hi All,
> I started with this issue because of my customer needs (max 25% voids) and
> argue with the EMS (one one the biggest) that its guide lines require 40%
> maximum of voids.
> In my opinion it should be included in the IPC-A-610 such as class 1, 2, 3
> and above class 3 such as 10% voids (using vapor phase), should be agreed
> between the two sides.
>
>
> On Fri, Dec 20, 2013 at 3:04 PM, David D. Hillman <
> *[log in to unmask]* <[log in to unmask]>> wrote:
> Hi Joyce - sometimes we can get too technical and over think a component.
> As you detailed, there can be a number of inputs to the equation but not
> necessarily. We have been using the 50% maximum void rule for 5 years on
> QFNs and I have only 2 cases where we had either a thermal or grounding
> issue that required us to maintain a smaller voiding percentage of the
> thermal pad.
>
> Dave
>
>
>
> From: Joyce Koo <*[log in to unmask]* <[log in to unmask]>>
> To: 'TechNet E-Mail Forum' <*[log in to unmask]* <[log in to unmask]>>,
> "'*[log in to unmask]* <[log in to unmask]>'" <
> *[log in to unmask]* <[log in to unmask]>>
> Date: 12/20/2013 06:45 AM
> Subject: RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
>
>
>
> Correct me if I am wrong, as for the thermal goes, there are many factors
> just the voiding. For example, the requirements of heat transfer path -
> vertical vs side, MCM possibly will have multiple grounds that may
> required isolation of heat path. If you allow 50% voids, depend upon the
> thermal via path, you might missing one sector of the MCM heat conduction
> path all together (if it is vertically channeled). It is not as easy as a
> single number. It is a bit of scary when the design is so far above the
> supply chain.
>
> Joyce Koo
> Researcher
> Materials Interconnect Lab
> Office: (519) 888-7465 79945
> BlackBerry: *(226) 220-4760* <%28226%29%20220-4760>
>
> -----Original Message-----
> From: TechNet [mailto:*[log in to unmask]* <[log in to unmask]>] On Behalf Of
> David D. Hillman
> Sent: Friday, December 20, 2013 7:36 AM
> To: *[log in to unmask]* <[log in to unmask]>
> Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
>
> Hi Reuven - I think that is a possible idea, however, what void percentage
>
> do you suggest and what technical data/investigative studies do you have
> to support the recommended void percentage? One thing to consider is that
> if a workmanship topic is missing from the JSTD-001/IPC-610 documents, it
> doesn't mean that the topic hasn't been reviewed. The IPC committees work
>
> hard to only put workmanship criteria in the specifications that is
> necessary and is supported by data. An example - the IPC-7093 BTC
> committee completed extensive efforts looking at the voiding of QFN
> thermal pads and found no industry consensus on a void percentage
> requirement. The JSTD-001 committee therefore has not included a maximum
> void percentage requirement in the 001 specification and the IPC-610
> specification shows no examples of voiding requirements of QFN thermal
> pads. The workmanship criteria show in the JSTD-001/IPC-610 specifications
>
> results in added costs to products and processes so the committees are
> very careful to not add requirements unless there is technical
> data/justification. I know a number of OEMs/CEMS who have a 50% maximum
> void requirement on the QFN thermal pad unless the component has specific
> thermal or electrical functional requirements. The IPC-7093 specification
> has some good information on the topic of BTC thermal pads and voids. The
> committees would welcome any investigative data on the topic too. Happy
> Holidays!
>
> Dave Hillman
> Rockwell Collins
> *[log in to unmask]* <[log in to unmask]>
>
>
>
> From: Reuven Rokah <*[log in to unmask]* <[log in to unmask]>>
> To: <*[log in to unmask]* <[log in to unmask]>>
> Date: 12/20/2013 12:48 AM
> Subject: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
> Sent by: TechNet <*[log in to unmask]* <[log in to unmask]>>
>
>
>
> Hi TechNets,
>
> I didn't see in the IPC-A-610E any acceptability reference in regards with
> the percentage of voids in solder joints of exposed thermal pads of QFNs
> or
> other components with exposed thermal pads.
>
> I recommend to add it in the next revision.
>
>
> --
>
> Best Regards,
>
> *Reuven Rokah*
>
> Mobile: 972-52-6012018
> Tel: 972-3-9360688
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