Hmm, interesting. Rockwell might be on to the proven and true, with safety factor of 2 to 3... or you are single chip (MCM) doing everything? If there are std coming out, better be forward looking (not say Rickwell is not... ;-(. ITRS white paper regarding the packaging for next 5-10 years might be a good start. Otherwise, the std of IPC might have to play a catch up game all the time. (wait until experience, data come out, rather FEM... which package/chip co-design to determine the minimum criteria... Of course, if the majority customer are mature market only, for CM, as example, the danger is good design might be busted, due to - std call out. Just take Paul's crazing as example... sad). My 1.8 cents.
Joyce Koo
Researcher
Materials Interconnect Lab
Office: (519) 888-7465 x79945
BlackBerry: (226) 220-4760
[cid:[log in to unmask]]
________________________________
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, December 20, 2013 8:05 AM
To: Joyce Koo
Cc: 'TechNet E-Mail Forum'
Subject: RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Hi Joyce - sometimes we can get too technical and over think a component. As you detailed, there can be a number of inputs to the equation but not necessarily. We have been using the 50% maximum void rule for 5 years on QFNs and I have only 2 cases where we had either a thermal or grounding issue that required us to maintain a smaller voiding percentage of the thermal pad.
Dave
From: Joyce Koo <[log in to unmask]>
To: 'TechNet E-Mail Forum' <[log in to unmask]>, "[log in to unmask]" <[log in to unmask]>
Date: 12/20/2013 06:45 AM
Subject: RE: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
________________________________
Correct me if I am wrong, as for the thermal goes, there are many factors just the voiding. For example, the requirements of heat transfer path - vertical vs side, MCM possibly will have multiple grounds that may required isolation of heat path. If you allow 50% voids, depend upon the thermal via path, you might missing one sector of the MCM heat conduction path all together (if it is vertically channeled). It is not as easy as a single number. It is a bit of scary when the design is so far above the supply chain.
Joyce Koo
Researcher
Materials Interconnect Lab
Office: (519) 888-7465 79945
BlackBerry: (226) 220-4760
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David D. Hillman
Sent: Friday, December 20, 2013 7:36 AM
To: [log in to unmask]
Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Hi Reuven - I think that is a possible idea, however, what void percentage
do you suggest and what technical data/investigative studies do you have
to support the recommended void percentage? One thing to consider is that
if a workmanship topic is missing from the JSTD-001/IPC-610 documents, it
doesn't mean that the topic hasn't been reviewed. The IPC committees work
hard to only put workmanship criteria in the specifications that is
necessary and is supported by data. An example - the IPC-7093 BTC
committee completed extensive efforts looking at the voiding of QFN
thermal pads and found no industry consensus on a void percentage
requirement. The JSTD-001 committee therefore has not included a maximum
void percentage requirement in the 001 specification and the IPC-610
specification shows no examples of voiding requirements of QFN thermal
pads. The workmanship criteria show in the JSTD-001/IPC-610 specifications
results in added costs to products and processes so the committees are
very careful to not add requirements unless there is technical
data/justification. I know a number of OEMs/CEMS who have a 50% maximum
void requirement on the QFN thermal pad unless the component has specific
thermal or electrical functional requirements. The IPC-7093 specification
has some good information on the topic of BTC thermal pads and voids. The
committees would welcome any investigative data on the topic too. Happy
Holidays!
Dave Hillman
Rockwell Collins
[log in to unmask]
From: Reuven Rokah <[log in to unmask]>
To: <[log in to unmask]>
Date: 12/20/2013 12:48 AM
Subject: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
Sent by: TechNet <[log in to unmask]>
Hi TechNets,
I didn't see in the IPC-A-610E any acceptability reference in regards with
the percentage of voids in solder joints of exposed thermal pads of QFNs
or
other components with exposed thermal pads.
I recommend to add it in the next revision.
--
Best Regards,
*Reuven Rokah*
Mobile: 972-52-6012018
Tel: 972-3-9360688
Fax: 076-5100674
<http://www.rokah-technologies.com/>[log in to unmask]
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