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May 2013

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From:
Robert Kondner <[log in to unmask]>
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Date:
Fri, 10 May 2013 13:07:32 -0400
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Hi,

 I agree and you bring up a good point.

 These percent coverage number are typically the % of nets on a board  that
have a test point. Even if you have 100% test point coverage that by no way
implies the board can be 100% tested. How many times do you see a .001uf cap
in parallel with a .1uf cap for good bypass? You cannot test if the .001uf
is present or missing. And a missing ..001uf might mean you have a noisy DDR
circuit.

 And for some nets with low value components you need 2 test point on nets
to support 3, 4, 5 and even 6 wire testing. (Various configurations of
Drive, Sense and Guard probes where each can have a sense pin.)

 I love ICT, I own a Teradyne Z-1820, but it can't catch everything. 

Bob K.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tontis, Theodore
Sent: Friday, May 10, 2013 12:39 PM
To: [log in to unmask]
Subject: Re: [TN] ICT Coverage

We strive for 100% coverage on all nodes that can be tested at ICT. This is
identified early on in the design phase (prototype) to insure we have the
necessary coverage and we have an assembly that is testable. 

Some of our recent designs use ICT to perform functional testing as soon as
the PCBA passes ICT. This has helped reduce the cost of our production test
systems and something we are going to continue to roll in on future designs.


Ted T.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Furrow, Robert
Sent: Thursday, May 09, 2013 3:25 PM
To: [log in to unmask]
Subject: [TN] ICT Coverage

Hi all,

I know the goal is "as much as possible", but what is a reasonable
expectation for % coverage during ICT for Class 2 products?

Thanks,
Bob Furrow
Quality Assurance Engineer
Honeywell Aerospace - Sarasota
941-360-6285
[log in to unmask]


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