We use vias in pad, plated over (vippo) in many designs.  They provide connectivity and heat conduction without adversely affecting the solder joint.  Especially important in the ground pad of QFNs.
"Plugged" or "capped" implies that a via is covered on only one side.  We do not use these because of concerns with nasty chemicals getting trapped inside during the fab or assembly processes.  
Vippos are usually made using the 2-step plating described in one of the other replies.  Drill vippos, plate, fill, planarize, drill non-vippos, plate.  Because of the added copper thickness, the line/space width on the exterior has limits.  It is also critical that the wrap plating meet the specs (mentioned in other reply).  Without this little bit of wrap plating, the stresses on the via can cause the cap to pop off and you'll have an open.  The planarization process seems primitive, and yet is critical.  This is the source of most problems.
Other tips:  do not use conductive filler, besides not helping that much, it messes up the copper plating.  Have these evenly distributed across the board; localized concentrations are difficult to planarize properly.  We were requested to have any specific drill size either all-vippos or all not.