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April 2013

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TechNet <[log in to unmask]>
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Date:
Thu, 4 Apr 2013 15:55:59 +0000
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TechNet E-Mail Forum <[log in to unmask]>, "MacFadden, Todd" <[log in to unmask]>
Subject:
Solder Stencil Interference due to Unintentional Via Fill
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"MacFadden, Todd" <[log in to unmask]>
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Hi everyone,

We are encountering some problems with HASL (SnPb) boards where many vias are coming in filled or partially-filled with solder. In some cases the solder protrudes enough to interfere with the SMT solder stencil process. The plant checked 10 incoming bare boards and all 10 had at least a few vias filled with solder protruding enough to cause problems.

I don't see anything in IPC-600 that would disqualify this condition. We don't specifically state in our drawing that closed vias are not allowed, but is there a standard that governs via fill/protrusions from the HASL finish?

Thanks for any insight.

Todd

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