IMHO, it depends what you mean by bubbles/voids. If they are a result of 
humidity being absorbed by hygroscopic contaminants through the coating 
(vesication or mealing) then the answer is a resounding 'not acceptable' 
under all conditions.

If they are the result of poor application of a liquid conformal coating 
or solder mask, I would say that they would not be acceptable if any of:
1. the substrate is not wetted under any bubble
2. a bubble bridges two bare conductors
3. a bubble occupies more than 30% of the space between two bare 
conductors with a potential difference of >10 V
4. there are more than 2 bubbles per square decimetre on either side, 
not counting the edges of a board where there are no conductors, up to 5 
mm from the edge
5. a void or bubble can be seen by 10 X visual inspection under a component
6. a paraxylylene coating displays any void

Some of the numbers in 3., 4. and 5. are arbitrary; common sense should 
be applied, along with the coating.

My 2 eurocents.

Brian

On 21.03.2013 17:18, Douglas Pauls wrote:
> OK, Minions, your next question in the quest to improve J-STD-001 and
> A-610 relates to bubbles in the conformal coating.
>
> I think we can all agree that the ideal conformal coating layer contains
> no bubbles or voids and is "purdy".    BUT:
>
> 1.  Are there bubbles in coatings in areas where they will not impact
> reliability and their presence should be viewed as a "Process Indicator"?
> If so, where and what limits would you use?
>
> 2.  What would you classify as a bubble requiring disposition, i.e.
> Becomes an actionable defect?  If so, where and why?
>
> 3.  Would any of your answers change depending on what KIND of coating it
> is, i.e. Acrylic vs. silicone vs. Parylene?
>
> Well, OK, that is three questions.  I'm on a roll.
>
>
> Doug Pauls
> Chairman, IPC Cleaning and Coating Committees
> Galactic Emporer
>
>
>
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