Hi Arlene,
To clarify, we don't supply panel layouts; rather we purchase the soldered assemblies as commodities and the CM picks the bare board house.
As I mentioned to Greg Smith, my team had concerns with the note as well. We don't really want to
allow intrusion into the board outline. It was suggested that we have the ME pre-define critical edges when they send us the shape, then
we'll specify no breakout along those edges, on the drill drawing, on a
board by board basis, and then we won't need these notes.
On the other hand, good CMs should know better than to design a singulation feature where there are components close by or overhanging. We'll probably handle this "edja-ma-cation" process through our overseas supplier engineer.
Many thanks,
Gary
>________________________________
> From: Arlene Fox <[log in to unmask]>
>To: 'Gary Koven' <[log in to unmask]>; "[log in to unmask]" <[log in to unmask]>
>Sent: Tuesday, February 12, 2013 3:28 PM
>Subject: RE: [DC] Board panelization techniques
>
>Hi Gary,
>
>I work for a CM that builds boards using customer supplied artwork as well as doing or own designs in house.
>
>I've had customers design their boards to fit an enclosure with no thought to manufacturing tolerances then
>expect the board to be manufactured to some ridiculously tight (impossible) tolerance to make it fit. From my
>perspective I'd say don't size the board to "just fit" the enclosure, give yourself some wiggle room, compensating
>for v-score and breakaway tabs then notes like these won't be necessary. If you need to add these notes to
>a drawing then you're not doing that.
>
>I do create the panel drawings for the board house so we don't end up with situations you've described.
>I always have routed edges where I have overhanging connectors and breakaway tabs are always placed in
>an open area, not under an overhanging part. I've created panels that combine v-score with routed edges and
>I always dimension the tab locations. I never leave those decisions to the board house, they don't know what
>works best for our processes.
>
>If you don't supply a panel layout you could always tell the CM you'd like to approve the panel prior to
>manufacturing.
>
>I've seen many designs in my 20+ years as a designer working for a CM, mostly good and well thought out, some
>not so much.
>
>Hope this helps and isn't too long winded.
>
>Arlene Fox, CID
>Enercon Technologies
>
>
>
>-----Original Message-----
>From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Gary Koven
>Sent: Tuesday, February 12, 2013 1:56 PM
>To: [log in to unmask]
>Subject: [DC] Board panelization techniques
>
>We've had several cases recently of boards not fitting into housings because the CM increased the board shape by one or both of the following improper panelization techniques:
>
>1) Adding material to round board edges to make flats so they could panelize, resulting in protrusions
>
>2) Breakaway tab design at or above board outline edges, resulting in protrusions
>
>Then, of course, they complain about having to rework the assembled boards in the areas they changed. You all may remember my recent post aboutthe same set of CMs that shaved the reverse mount LED pads and then complained about rework in the areas they changed. Similar song, different day.
>
>
>Not wishing to have to prepare a panelization drawing for every board, after going through a number of IPC specs and not finding a clear definition to call out on a drill drawing, I've come up with two proposed boilerplate notes:
>
>"BREAKAWAY TABS MUST SHEAR BELOW EDGE OF GERBER BOARD OUTLINE USING LOW STRESS MOUSE BITE BREAKAWAY TAB PATTERN WITH NO PROTRUSION BEYOND EDGE."
>
>"V-SCORE LINES MUST SHEAR AT OR BELOW EDGE OF GERBER BOARD OUTLINE WITH NO PROTRUSION BEYOND EDGE."
>
>
>They also have a habit of placing breakaway tabs and score lines at edges near overhanging connectors, causing failure when the mating connector cannot fully engage due to the added material. In this case, I've had to revise the drill drawings graphically and annotatively to specifically prohibit tab or score design.
>
>Any IPC references I missed, and/or suggestions for improving yield that are better than what I propose, please comment.
>
>
>TIA and Best Regards,
>
>Gary M. Koven, C.I.D.
>InVue Security Products
>
>Charlotte, NC, USA
>Board Of Directors, RTP Chapter
>
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