Thanks to all...

The SMTA Guideline Rev C from ten years ago recommends .040 pads on .100
centers
(as do many other sources all down through recent history)
It makes me wonder if people are just echoing the old guideline,
or if the defaults still apply
but I've received several other guidelines from people DOING the work that
make statements like

“Ideally, the largest test pads used along with 100mil test probes
provides the most repeatable and cost effective solution. In practice,
0.035” bottom side test pads with 0.070” minimum center to center
spacing are used successfully and are considered a standard by many.”

That's just one example, and of course even that would change on a dense
design,
using higher cost probes and guided probe fixtures, etc
but it led me to wonder if the default guidelines had been updated,
so THANKS for sharing your experience.
I want to be practical, and some of our designs are getting more dense

If you are willing to address one more factor:
What clearance do you set between probe body and component body?
(or from probe center to component body, if that is more common?)

Jack


On Thu, Feb 28, 2013 at 9:39 AM, Dave Schaefer <[log in to unmask]>wrote:

> Jack,
>
> I don't currently have the most recent copy of that standard either.
>
> What I can mention is that regardless of the minimum size listed in the
> standard manufacturing groups always prefer to develop more robust test
> systems; larger pads with greater pitch allows for use of test pins which
> last longer (pretty certain this isn't breaking news to you).
>
> When working at a large OEM our local testability standard was to provide
> 0.040" pads on 0.100" pitch wherever possible. Pad sizes and pitches were
> reduced first locally then globally to as low as 0.030" @0.050" centers.
> Fixtures employing smaller features required frequent maintenance and
> replacement. Test strategy was 100% nodal coverage via ICT and the fit was
> good for the technology level of the products.
>
> The vast majority of designs I am currently working on are impossible to
> achieve 100% coverage rendering pure ICT ineffective. Providing ICT access
> to connectors, power rails, and JTAG for functional testing as well as AOI
> and AXI is the best solution for these higher density designs.
>
> Hth,
> Dave
>
>
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