Hi Denny,
Based on your inquiry we are planning to run a set of IST coupons with solder filled holes and compare the results to similar coupons without solder in the holes.
What we will do is to take a panel of IST coupons and block off with Kapton tape the holes on some of the coupons and leave off the tape on other coupons. We will then subject the coupons to a wave soldering making sure the coupons without tape are solder filled. We will precondition the coupons to lead free temperatures (6X260°C) and then subject the coupon to thermal excursion to 150°C until we have 50% failure rate or more.
I'll get back to you (and TechNet) with the results when the test is complete.
Sincerely,
Paul Reid
Program Coordinator
PWB Interconnect Solutions Inc.
235 Stafford Rd., West, Unit 103
Nepean, Ontario Canada, K2H 9C1
613 596 4244 ext. 229
Skype paul_reid_pwb
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Dennis Fritz
Sent: January 2, 2013 12:31 PM
To: [log in to unmask]
Subject: Re: [TN] reliability test for PCBs
I too have wondered if there is a correlation between performance of solder filled vias and bare copper board unfilled vias? A couple years ago, I asked three testing houses whether there was a correlation and got two yes answers and one no answer.
Of course the thermal cycle is differenf from -55C to +125C on solder filled vias from the room temperature (20C? to 250C) cycling of bare copper. The 250C would melt out all the solder in the filled holes. But, does anyone know of a correlation between the methods?
Denny Fritz
-----Original Message-----
From: Joyce Koo <[log in to unmask]>
To: TechNet <[log in to unmask]>
Sent: Wed, Jan 2, 2013 10:52 am
Subject: Re: [TN] reliability test for PCBs
One additional note: Filled PTH (after assembly) thermal shock should be used if
ou decided to use -55 to +150. 10 cycle as burn-in normally used (old old old
ays). Un-filled copper barrel are flexible some what, you may passed thermal
hock and got false security at PWA level. (depend upon where are the delam
appened: - barrel separation, you need filled. Copper ductility issue,
n-filled might be better). My out dated 2 cents.
Joyce Koo
aterials Researcher - Materials Interconnect Lab
esearch In Motion Limited
ffice: (519) 888-7465 79945
obile: (226) 220-4760
-----Original Message-----
rom: TechNet [mailto:[log in to unmask]] On Behalf Of Scott A. Bowles
ent: Wednesday, January 02, 2013 9:29 AM
o: [log in to unmask]
ubject: Re: [TN] reliability test for PCBs
It depends if you are trying to test against a standard for PTH structural
ntegrity to determine if the boards will withstand multiple thermal cycles
hrough assembly, rework or repair or if you are trying to test more for
ong-term reliability against end-use thermal cycles. The industry standard at
he bare board manufacturer level is to perform one thermal stress so you can
low down to your supplier to perform thermal stress testing per IPC-6012
ection 3.6.1.1 IAW IPC-TM-650, Method 2.6.8, test Condition "A" (288C for 10
econds) per the number of cycles you deem appropriate for your assembly
rocess, e.g., double-sided SMT (2), PTH components (1), rework (2), maybe five
ycles. Your printed board suppliers should be capable of performing this test
or you.
If you are also or more concerned with PTH structural integrity surviving
nd-use requirements then you could specify Thermal Shock as Joyce suggested but
ou don't randomly use -55 to 150C, you need to specify a test condition per
able 1 of IPC-TM-650, Method 2.6.7.2, based on material type. This test is
onsidered a special requirement per Table 4-3 of IPC-6012 and will probably
ave to be performed by an independent test lab, not done by bare printed board
upplier (extra time and cost). You also probably need to flow down the
equirement to have the board supplier to ensure to add test coupon "D" to the
anufacturing panels for this test.
Regards,
Scott A. Bowles
ffice: 513-943-2483
obile: 513-208-9009
-----Original Message-----
rom: TechNet [mailto:[log in to unmask]] On Behalf Of Ramakrishnan Saravanan
ent: Tuesday, January 01, 2013 11:10 AM
o: [log in to unmask]
ubject: Re: [TN] reliability test for PCBs
Dear all,
The test method 2.4.13.1 specifies test method that is designed to determine
he thermal integrity of unclad or metallic clad laminates using short-term
older exposure. My interest is to find the toughest know standard for PTH
ntegrity. regards,
.Saravanan
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