See attached JEDEC Mechanical Outline for DDR3 DIMM memory module. Page 17 shows recommended plating and Ni barrier.

 


Jim McGrath
Strategic Marketing Manager
TE Consumer Devices
Cell: 630-244-3872
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D.
Sent: Monday, October 22, 2012 2:40 PM
To: [log in to unmask]
Subject: Re: [TN] Ni barrier thickness

No, that information belongs on the SCD for the component.
There are so many different applications with different requirements so there is no standard that could cover them all.
Even PWBs plated with gold must have the exact dimensions/methods documented on the fabrication drawing if they are outside of the ENIG standard.
However, there are some plating specifications in the JEDEC component standards.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ioan Tempea
Sent: Monday, October 22, 2012 2:33 PM
To: [log in to unmask]
Subject: [TN] Ni barrier thickness

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Dear Technos,

For applications other than ENIG, like, for instance, gold plated Cu pins, is there any standard (ASTM?) specifying the thickness of the Ni barrier that would prevent Cu diffusion towards the surface?

Thank you,

Ioan Tempea, ing.
Ingénieur principal de fabrication / Senior Manufacturing Engineer [signature002]<http://www.digico.cc/>

950 RUE BERGAR, LAVAL, QC, H7L 5A1<http://g.co/maps/2gh3f>
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Entreprise manufacturière / Gestion du capital humain


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