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September 2012

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Subject:
From:
Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Joyce Koo <[log in to unmask]>
Date:
Wed, 19 Sep 2012 20:36:07 +0000
Content-Type:
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text/plain (175 lines)
May be your "small expensive friends" should do a thermal shock 5 or 10 times prior to assembly to eliminate the problem at PWB level.  (fly probe before and after).  
Good old days, all the high end stuff are pre-screened at batch level prior to assemble and "burn-in" thermal shock 10 times prior to ship to root out any early failure = usually at developing stage, not MFG stage).  Exactly try to avoid expensive mistake later, (was replaced later by a coupon on pwb with (1) finest feature (2) weakest location (3) new features and (4) testable electrically at functional level somewhat, not cheap, but cheaper than risk at assembly level).  Follow the rule of "pay me now and pay me less, or Pay me later and pay me more - usually 10X, if not 100X<  more with debug FA add on and time loss on delivery.  

Joyce Koo
Materials Researcher - Materials Interconnect Lab
Research In Motion Limited
Office: (519) 888-7465 79945
Mobile: (226) 220-4760

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
Sent: Wednesday, September 19, 2012 3:41 PM
To: [log in to unmask]
Subject: Re: [TN] Broken Vias

Amol,

 Good Questions, I will find out.

Thanks,
Bob K.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Amol Kane
(Asteelflash,US)
Sent: Wednesday, September 19, 2012 3:30 PM
To: [log in to unmask]
Subject: Re: [TN] Broken Vias

Were the boards moisture baked before assembly? .....is the stackup
balanced? Is the via damage more pronounced in the area of warpage?


Amol Kane
Process Engineer
AsteelFlash US East Corp
Tel:   (607) 687.7669 x349 (O)
www.asteelflash.com


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-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
Sent: Friday, September 14, 2012 5:02 PM
To: [log in to unmask]
Subject: Re: [TN] Broken Vias

Hi,

 Does anyone know about the TCE of via plug material? I am trying to get a
material number of what was used. This was the first board we ever ran with
via plugging but I would think that is a well-known process?

Bob K.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jason Zhao
Sent: Friday, September 14, 2012 12:52 PM
To: [log in to unmask]
Subject: Re: [TN] Broken Vias

Bob,

Xsection will show you where the opens occur. Possibilities are: copper
plating folds; thin copper; corner crack; post separation; separation due to
no wraparound; etc. Then we can determine the root causes from there (there
are too many to guess now). Looking forward to some pictures.

Best Regards

Jason Zhao
VP of North America Operations
Sunshine Circuits
3400 Silverstone Drive, Suite 139, Plano, TX 75023 US Cell 510-468-4412,
China Cell 131-62722392 www.sunshinepcbgroup.com

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
Sent: Friday, September 14, 2012 10:18 AM
To: [log in to unmask]
Subject: [TN] Broken Vias

Hi,

 

A small company in the area has a board with two very expensive parts, about
$3K each part. They built 30 boards and had lots of open via connections.
They are getting cross sections now on some bad vias. In addition to many
bad vias there was some board warp. Sorry I don't have any hard numbers on
bad via counts or warp.

 

These were 10 mil holes in .062 material, a 6:1 aspect ratio, should be
easy. Vias were plugged and plated so they could be used as flying probe
test points. 

 

After reflow assembly the boards were run on a wave machine using a mask
where about 25% of the board was exposed to the wave. Everything lead free. 

 

Question:

 

Can folks suggest lists of items we can check, measure or inquire into? Any
guesses or ideas as what might be going on?

 

Thanks,

Bob K.



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