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September 2012

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From:
Robert Kondner <[log in to unmask]>
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Date:
Fri, 21 Sep 2012 18:27:28 -0400
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Hi,

 I am really trying to find reasons why a run of boards with filled vias
ended up with bad vias. If this solid copper plane does indeed block vapor
then that is a possibility.

 As for lower pressure, I don't know if lower air pressure will
significantly increase diffusion rates through laminate. Maybe someone else
can comment?

 Thanks again for all your ideas.

Bob K.


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of SALA GABRIELE
Sent: Friday, September 21, 2012 5:42 PM
To: [log in to unmask]
Subject: [TN] R: [TN] R: [TN] Bake time for boards with multiple solid
copper planes

Bob,

mmm....yours is an hard cake to cook .. :-(

..... but remember,  the moisture , along the time, could get inside also
trough sides of PCB, it will take time but it will happen.

BTW, you could investigate to Bake PCBs under Vacuum. I never used such
method but I heard about it.  Moisture (H2O) boils at lower temperature and
vacuum should help the vapour to escape out . May be ? .... :-))

Gabriele


-----Messaggio originale-----
Da: Robert Kondner [mailto:[log in to unmask]]
Inviato: venerd́ 21 settembre 2012 23.19
A: 'TechNet E-Mail Forum'; 'SALA GABRIELE'
Oggetto: RE: [TN] R: [TN] Bake time for boards with multiple solid copper
planes

Gabriele,

  Thank you, I did start looking and reading.

 Problem is the bake out time for a 10cm square of a laminated with copper
coated top and bottom is something like 2 years. (From the NRL video.)
 
 Seems like copper is impenetrable by water vapor. I would assume water in
absorbed by the laminate during the  manufacturing process so it will exist
between solid copper planes. And filling the vias probably makes it even
worse.

 Have not been able to verify any of this yet, it was only through the NPL
link that I came to this conclusion.

 If vias are tied to plane using thermal reliefs, and not flooded, then that
makes a board "Bake-able" as vapor can escape.

 Any thoughts from anyone would be appreciated.

Bob K.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of SALA GABRIELE
Sent: Friday, September 21, 2012 3:32 PM
To: [log in to unmask]
Subject: [TN] R: [TN] Bake time for boards with multiple solid copper planes

Hi Bob,

suggestion, read (and study):

IPC-1601 Printed Board Handling and Storage Guideline
http://www.ipc.org/TOC/IPC-1601.pdf (abstract) 

see chapters

3.4 Baking for Moisture Removal
3.4.1 Problems Caused By Baking
3.4.2 Baking Environment
3.4.3 Baking Considerations
3.4.4 Establishing Baking Profiles
Ecc....

Also take a look to Test Method  IPC-TM-650 2-6-28 (free download), useful
TM that will help you to better assess what it means moisture entrapped in
laminate and how to remove it totally, or partially according to your
specifications.

Moisture Content and/or Moisture Absorption Rate, (Bulk) Printed Board
http://www.ipc.org/4.0_Knowledge/4.1_Standards/test/2-6_2-6-28.pdf

by experience, in the past, to bake-off PCB from 16 Layers up to 28 L and
more, after about 14-18 months of shelf, even if well packed, we use to bake
them at 115°C  for 16 h, some time 18 h or 24 h, depending of thickness,
size and weight and a general assessment about % of resin content versus
fiber-glass (construction and stake-up +Copper content).
Some time, to protect of OSP finish, we use to blow N2 inside the ventilated
Oven  

Important: no need to remove all the moisture entrapped, but just the enough
MAMC (Maximum Acceptable Amount Content).

Other suggestion, when staking PCB inside oven, pile them up at a maximum
height of 25 mm ( 1 inch), in such way the vapour flows out easily. 

Have a good luck

Gabriele

-----Messaggio originale-----
Da: TechNet [mailto:[log in to unmask]] Per conto di Robert Kondner
Inviato: venerd́ 21 settembre 2012 19.04
A: [log in to unmask]
Oggetto: [TN] Bake time for boards with multiple solid copper planes

Hi,

 

Can anyone point me to a document that describes how moisture can be driven
out of internal PCB layers if solid copper layers exist above and below
internal layers?

 

When routing PCB connections to internal layers, say GND for example, you
want to tie together multiple GND plane layers. But unless a thermal
connection is provided I see no way for moisture to escape from internal
layers.

 

Using thermal vias breaks up GND planes so it is common to flood vias. 

 

Question:

 

  Do flooded vias to multiple layers raise problems with bake out?

 

Bob K



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