Joyce
Perhaps I am not communicating well enough.
Te question was not about solder bumping in general.,
It was about 50u spaced solder bumps.
The RTI paper specified that only electroplating would do it.
I thought your original point was that closer solder joint spacings are possible.
But what does this have to do with stencil deposition and reflow, which are the
essence of SMT.
--- On Tue, 8/28/12, Joyce Koo <[log in to unmask]> wrote:
From: Joyce Koo <[log in to unmask]>
Subject: Re: [TN] "end of solder"--a clarification (in the context of tin mining downsides)
To: "[log in to unmask]" <[log in to unmask]>, "[log in to unmask]" <[log in to unmask]>
Date: Tuesday, August 28, 2012, 2:56 PM
Harvey, there are many methods for solder bumping. Stencil print is the lowest grade. You can use preform, solid sphere with flux, or laser attach shot with a gun. It is all performance
and cost volume driven. You can spend few hours on web to catch up. By the way, I like vintage wine, forget dew (sorry, wine just too difficult to resist. I open my big mouth again. :-(
--------------------------
Sent using BlackBerry
From: harvey [mailto:[log in to unmask]]
Sent: Tuesday, August 28, 2012 05:16 PM
To: Joyce Koo; 'TechNet E-Mail Forum' <[log in to unmask]>
Subject: RE: [TN] "end of solder"--a clarification (in the context of tin mining downsides)
An additional reply, Joyce., and a question.
2 mil solder bump sapcing described in the RTI paper (thanks for the ref) is indeed interesting and important. .Are those dimensions also attainable with
stencil deposition and reflow?
The RTI paper stipulates electroplating deposition.
--- On Tue, 8/28/12, Joyce Koo <[log in to unmask]> wrote:
From: Joyce Koo <[log in to unmask]>
Subject: RE: [TN] "end of solder"--a clarification (in the context of tin mining downsides)
To: "[log in to unmask]" <[log in to unmask]>, "[log in to unmask]" <[log in to unmask]>
Date: Tuesday, August 28, 2012, 11:50 AM
250 micron? Harvey, what generation you are? Getting old? This is 2006 vintage:
http://www.ewh.ieee.org/soc/cpmt/presentations/cpmt0609a.pdf
Joyce Koo
Materials Researcher - Materials Interconnect Lab
Research In Motion Limited
Office: (519) 888-7465 79945
Mobile: (226) 220-4760
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of harvey
Sent: Tuesday, August 28, 2012 2:25 PM
To: [log in to unmask]
Subject: Re: [TN] "end of solder"--a clarification (in the context of tin mining downsides)
Richard
I specifically said below 1/4 mm solder joints.
Where is the path forward?
Correction in my text--it should have been SIP--System-in-Package, one of the paths forward. Isn't it interesting that after all of the hullaballew about MCMs in the early 1990s,
that they might be coming back again.
They were shelved by array packaging, including flip chips, and by SMT on 2 sides.
Those met density needs for 2 decades.
Intel shelved BBUL also, 10 years ago.
--- On Tue, 8/28/12, Stadem, Richard D. <[log in to unmask]> wrote:
From: Stadem, Richard D. <[log in to unmask]>
Subject: Re: [TN] "end of solder"--a clarification (in the context of tin mining downsides)
To: [log in to unmask]
Date: Tuesday, August 28, 2012, 9:49 AM
Solder joint spacings of .010" (1/4thmm) or less are very common today.
Printing solder paste through .006" diameter apertures is also done.
You do need different materials and process know-how.
Laser soldering is a wonderful technique for VFP microvia formation as well as for subminiature soldering.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of harvey
Sent: Tuesday, August 28, 2012 11:33 AM
To: [log in to unmask]
Subject: [TN] "end of solder"--a clarification (in the context of tin mining downsides)
Well, of course solder will not go away, nor will SMT assembly.
Neither the reliability issues presented by lead-free solder usage nor dirty tin mining are basic reasons for their future decline in electronic manufacturing.
But as solder joint spacings are forced below 1/4th mm by lead density in the <20 nM IC lithography era, how will we be able to screen and reflow the old way?
Intel's BBUL pointed one direction to the future, in my opinion.
It was motivated by the fragility of low K dielectric layers as well as need for higher density That was over 10 years ago when 65 nM litho was on the horizon.
Features included laser drilled vias and copper plated connections to IC lands, no solder balls.Those are precisely how embedded chips, passive and active, are assembled.
The possible impllications for electronic manufacring might be examined. They might include resurrection of MCMs, now called SPs. Fab and assembly would be merged.
There are lots of possibilities. Should we not begin to explore them?
] Bumpless Build-Up Layer PackagingAdobe PDFBumpless Build-Up Layer Packaging Steven N. Towle, Henning Braunisch, Chuan Hu, Richard D. Emery, and Gilroy J. Vandentop Intel Corporation Components Researchwww.sigrity.com/papers/asme
It ______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or
[log in to unmask] ______________________________________________________________________
______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or
[log in to unmask]
______________________________________________________________________
______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or
[log in to unmask]
______________________________________________________________________
---------------------------------------------------------------------
This transmission (including any attachments) may contain confidential information, privileged material (including material protected by the solicitor-client or other applicable privileges), or constitute non-public information. Any use of this information
by anyone other than the intended recipient is prohibited. If you have received this transmission in error, please immediately reply to the sender and delete this information from your system. Use, dissemination, distribution, or reproduction of this transmission
by unintended recipients is not authorized and may be unlawful.
---------------------------------------------------------------------
This transmission (including any attachments) may contain confidential information, privileged material (including material protected by the solicitor-client or other applicable privileges), or constitute non-public information. Any use of this information by anyone other than the intended recipient is prohibited. If you have received this transmission in error, please immediately reply to the sender and delete this information from your system. Use, dissemination, distribution, or reproduction of this transmission by unintended recipients is not authorized and may be unlawful.
______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or [log in to unmask]
______________________________________________________________________
|
