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From:
"Stadem, Richard D." <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Stadem, Richard D.
Date:
Tue, 28 Aug 2012 14:00:21 -0500
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LOL. Good choice, Joyce.
Yes, most of us are well past the old SMT, this is the new. But of course, the old SMT will be around for a few more years.
Maybe.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Joyce Koo
Sent: Tuesday, August 28, 2012 1:51 PM
To: [log in to unmask]
Subject: Re: [TN] "end of solder"--a clarification (in the context of tin mining downsides)

250 micron?  Harvey, what generation you are?  Getting old?  This is 2006 vintage: 
http://www.ewh.ieee.org/soc/cpmt/presentations/cpmt0609a.pdf


Joyce Koo
Materials Researcher - Materials Interconnect Lab Research In Motion Limited
Office: (519) 888-7465 79945
Mobile: (226) 220-4760

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of harvey
Sent: Tuesday, August 28, 2012 2:25 PM
To: [log in to unmask]
Subject: Re: [TN] "end of solder"--a clarification (in the context of tin mining downsides)

Richard
I specifically said below 1/4 mm solder joints.
Where is the path forward?

Correction in my text--it should have been SIP--System-in-Package, one of the paths forward. Isn't it interesting that after all of the hullaballew about MCMs in the early 1990s, that they might be coming back again.
 
They were shelved by array packaging, including flip chips, and by SMT on 2 sides.
Those met density needs for 2 decades.
 
Intel shelved BBUL also, 10 years ago.
 
 

--- On Tue, 8/28/12, Stadem, Richard D. <[log in to unmask]> wrote:


From: Stadem, Richard D. <[log in to unmask]>
Subject: Re: [TN] "end of solder"--a clarification (in the context of tin mining downsides)
To: [log in to unmask]
Date: Tuesday, August 28, 2012, 9:49 AM


Solder joint spacings of .010" (1/4thmm) or less are very common today.
Printing solder paste through .006" diameter apertures is also done. 
You do need different materials and process know-how.

Laser soldering is a wonderful technique for VFP microvia formation as well as for subminiature soldering.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of harvey
Sent: Tuesday, August 28, 2012 11:33 AM
To: [log in to unmask]
Subject: [TN] "end of solder"--a clarification (in the context of tin mining downsides)

Well, of course solder will not go away, nor will SMT assembly.
Neither the reliability issues presented by lead-free  solder usage nor dirty tin mining are basic reasons for their future decline in electronic manufacturing.

But as solder joint spacings are forced below 1/4th mm by lead density in the <20 nM IC lithography era,  how will we be able to screen and reflow the old way?

Intel's BBUL pointed one direction to the future, in my opinion. 
It was motivated by the fragility of low K dielectric layers as well as need for higher density That was over 10 years ago when 65 nM litho was on the horizon.

Features included laser drilled vias and copper plated connections to IC lands, no solder balls.Those are precisely how embedded chips, passive and active, are assembled.

The possible impllications for electronic manufacring might be examined.  They might include resurrection of MCMs, now called SPs. Fab and assembly would be merged.
There are lots of possibilities.  Should we not begin to explore them?

 
] Bumpless Build-Up Layer PackagingAdobe PDFBumpless Build-Up Layer Packaging Steven N. Towle, Henning Braunisch, Chuan Hu, Richard D. Emery, and Gilroy J. Vandentop Intel Corporation Components Researchwww.sigrity.com/papers/asme

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