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Subject:
From:
Tan Geok Ang <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Tan Geok Ang <[log in to unmask]>
Date:
Mon, 2 Jul 2012 02:26:49 +0000
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Easiest way....Vapour Phase with vacuum? 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of grandrien
Sent: Saturday, 30 June 2012 4:51 PM
To: [log in to unmask]
Subject: Re: [TN] I'm back and have a question about QFN voids

Hi ed,

Is your solution to solder the central pad through a PTH on soldeing wave ?
It seems me very tricky process.

Why not using 
- preform 
- or distributed vias through the central pad to allow the flux outgasing. In that case to avoid the overflow of solder through the vias on the opposite PCB side, printed paste around vias, not on them, and add solder mask rings around the vias to contain the solder. out of the vias.

QUESTION: requirements on void max are quite always often between 20-30%. But looking at thermal studies from different actors such as component manufacturers or even OEM or CEM it seems in very most cases the thermal impact keeps quite negligeable up to 70-80% and sometime more. 
So why everyone keeps the 20-30% requirement ?
Or some of you accept  higher void levels under QFN ?

========================================
Message du 29/06/12 19:04
De : "Ed Popeielarski" 
A : [log in to unmask]
Copie à : 
Objet : [TN] I'm back and have a question about QFN voids

Greetings 'netters,

For the past 2 1/2 years I've been lurking because Technet didn't get along with my employer's email system (specifically during maintenance).

I solved that problem by finding another employer! See how much you guys mean to me?!

It's good to be "back in the saddle again", so please allow me to begin with a perplexing question:

I need to solve QFN ground-pad voiding on a 0.038" thick ENIG assembly. The application is a high power RF amp and voiding as low as 25% causes issues with reliability.

Many attempts to resolve this with stencil variations, (thickness, star patterns, etc) and process variables (reflow time/temps) have been fruitless.

I'm considering re-spinning the board with a via dead center of this 6mm part, print & reflow only the leads, then wave solder the via (SAC305 with water soluble flux) in hopes of forcing the volatiles out from the center due to the wetting forces. Has anyone tried and succeeded with this method or am I sailing off the edge of the planet?

Thanks for your help in advance.


Ed Popielarski
Engineering Manager

Technical Services, Inc.
970 NE 21st Ct.
Oak Harbor, Wa. 98277

Ph: 360-675-1322
Fx: 206-624-0965
Cl: 949-581-6601

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