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July 2012

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Subject:
From:
Phil Bavaro <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Mon, 2 Jul 2012 15:57:48 -0700
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Ed,

Welcome back!  I know the feeling.

I have seen high volume production requiring J-STD-001 Class 2 with as much as 40 percent voiding survive just fine but I have also experienced Class 3 military assemblies which claimed to require less than 10 percent voiding.  If you say you need less than 10% then that is your requirement.  

Currently I have QFNs on Class 3 assemblies which have all the vias under the part belly filled with epoxy and cap plated over which naturally reduces the voiding.  There is some debate as to what paste pattern optimizes the lack of voids, and I have experimented with all kinds of paste shapes.  

I believe that wavesoldering a single via will not accomplish what you desire and most likely will cause a myriad of other issues that you should want to avoid.  

Here is another approach that you might consider:

Pretin the device so that the belly already has solid solder available to melt.  Print paste in the corners of the belly pad, and place and reflow.  The trick is to not apply too much solder during pretinning as to cause misalignment in reflow.  Voiding is initiated at the location of the printed paste so minimizing the print area leads to minimizing void potential.  Eliminating voids is always a controversial subject so you picked a good one to enter back into the forum with.

My $.02 worth.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D.
Sent: Monday, July 02, 2012 3:22 PM
To: [log in to unmask]
Subject: Re: [TN] I'm back and have a question about QFN voids

The 25% max void criteria applies to BGAs. I don't think there is any hard/fast requirement for voids in QFN devices, but I'm not sure. However, your QFN may not work properly if you have even 10% voiding in some cases. It depends on the component requirements and the design. You may need <10% max loss of solder connection between the belly pad and the matching pad on the PWB in order to provide the required thermal transfer or to provide sufficient electrical connection (or both!). 
________________________________________
From: TechNet [[log in to unmask]] On Behalf Of grandrien [[log in to unmask]]
Sent: Monday, July 02, 2012 4:12 PM
To: [log in to unmask]
Subject: Re: [TN] I'm back and have a question about QFN voids

That is rigth, vacuum is an option, except if you have quite high volume production ?
Nevertheless are you sure a max of 25% void is really necessary?


========================================
Message du 02/07/12 13:18
De : "Braddock, Iain (UK)"
A : [log in to unmask]
Copie ŕ :
Objet : Re: [TN] I'm back and have a question about QFN voids

Absolutely......problem solved!

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tan Geok Ang
Sent: 02 July 2012 03:27
To: [log in to unmask]
Subject: Re: [TN] I'm back and have a question about QFN voids

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Easiest way....Vapour Phase with vacuum?

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of grandrien
Sent: Saturday, 30 June 2012 4:51 PM
To: [log in to unmask]
Subject: Re: [TN] I'm back and have a question about QFN voids

Hi ed,

Is your solution to solder the central pad through a PTH on soldeing wave ?
It seems me very tricky process.

Why not using
- preform
- or distributed vias through the central pad to allow the flux outgasing. In that case to avoid the overflow of solder through the vias on the opposite PCB side, printed paste around vias, not on them, and add solder mask rings around the vias to contain the solder. out of the vias.

QUESTION: requirements on void max are quite always often between 20-30%. But looking at thermal studies from different actors such as component manufacturers or even OEM or CEM it seems in very most cases the thermal impact keeps quite negligeable up to 70-80% and sometime more.
So why everyone keeps the 20-30% requirement ?
Or some of you accept  higher void levels under QFN ?

========================================
Message du 29/06/12 19:04
De : "Ed Popeielarski"
A : [log in to unmask]
Copie ŕ :
Objet : [TN] I'm back and have a question about QFN voids

Greetings 'netters,

For the past 2 1/2 years I've been lurking because Technet didn't get along with my employer's email system (specifically during maintenance).

I solved that problem by finding another employer! See how much you guys mean to me?!

It's good to be "back in the saddle again", so please allow me to begin with a perplexing question:

I need to solve QFN ground-pad voiding on a 0.038" thick ENIG assembly. The application is a high power RF amp and voiding as low as 25% causes issues with reliability.

Many attempts to resolve this with stencil variations, (thickness, star patterns, etc) and process variables (reflow time/temps) have been fruitless.

I'm considering re-spinning the board with a via dead center of this 6mm part, print & reflow only the leads, then wave solder the via (SAC305 with water soluble flux) in hopes of forcing the volatiles out from the center due to the wetting forces. Has anyone tried and succeeded with this method or am I sailing off the edge of the planet?

Thanks for your help in advance.


Ed Popielarski
Engineering Manager

Technical Services, Inc.
970 NE 21st Ct.
Oak Harbor, Wa. 98277

Ph: 360-675-1322
Fx: 206-624-0965
Cl: 949-581-6601

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