Absolutely! Thank you. I've gained quite a bit of knowledge from this thread.

Craig Sullivan
Manufacturing Engineer
MPL Incorporated
P: 607.266.0480
F: 607.266.0482
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
Sent: Friday, July 13, 2012 4:15 PM
To: [log in to unmask]
Subject: Re: [TN] Through hole barrel voids

Hi Jack!

Thank-you for sharing this with the group! This is definitely going into my reference folder!

I can imagine that Craig would be giving you a big high-five for this too!

Steve

-----Original Message-----
From: Jack Crawford
Sent: Friday, July 13, 2012 3:39 PM
To: [log in to unmask]
Subject: Re: [TN] Through hole barrel voids

About 13 years ago, before Revision C to J-STD-001 and IPC-A-610, the task groups were struggling to resolve comments for hole fill requirements. The leader of the IPC Assembly and Joining committee at that time was Jim Maguire, then at Boeing and moved on to Intel. Jim pulled together a bunch of pages (224 to be exact) about hole fill from publications and technical presentations by industry experts. We scanned them to a pdf file way back when so they are images only--not searchable text. They can be downloaded from http://files.ipc.org/HoleFill-complete.zip

When referring to the hole fill criteria in J001 and 610, it's important to remember that the criteria is intended as visual assessment--what are the visible levels of solder within the hole. 75% fill means that there is no more than 25% of visible barrel space (counting both top and bottom). It was not intended and it is not appropriate to state that 75% fill requirement is related to total volume of solder.

The topic of voids within the solder in the barrel--not visible without x-ray or destructive analysis--has been discussed at IPC committee meetings. 
More than one person has made the statement that voids within a solder connection, including inside the solder in barrels, actually provides stress release for the surrounding areas.

There is no current industry consensus on the maximum amount of voiding that should be acceptable in solder mass within a barrel, in a BGA ball, or within the solder between two flat surfaces (bottoms of BTC, gull wing leads, chip components, etc.). Having followed these discussions for the 15 years I've been in IPC committee meetings, it's obvious that there are a lot of opinions and even some good test data. Some of the Class 3 avionics and weapon system manufacturers in particular want the conservative approach (lower void levels) so it's been hard to move away from the 25% in BGA balls and nothing has been established for other connections.

Regarding voids within PTH, I sometimes suggest to users that they find the oldest functioning through-hole assembly they can find (some military systems are 30-40 years old) and x-ray the assembly to see how much voiding is in the holes. Find the connections with the largest void area in connections that have not failed and measure. That isn't necessarily an indicator of how much void will never fail, but I believe anyone that does this will be surprised to see how many voids & the size of the voids that have been in the products for decades without failure.

Jack Crawford
IPC Director Certification and Assembly Technology IPC International Inc.
3000 Lakeside Dr. Suite 309S
Bannockburn, IL 60015
847-597-2893
Fax 847-615-5693
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