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June 2012

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Subject:
From:
Craig Sullivan <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Craig Sullivan <[log in to unmask]>
Date:
Fri, 29 Jun 2012 14:48:51 -0400
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Same here...  We stay 50-55%, preferably 50.
I'm not sure if we really gain anything by it , but I also have the stencil house align the window-panes such that no paste is printed directly into the vias. 

Craig Sullivan
Manufacturing Engineer
MPL Incorporated
P: 607.266.0480
F: 607.266.0482
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David D. Hillman
Sent: Friday, June 29, 2012 2:14 PM
To: [log in to unmask]
Subject: Re: [TN] I'm back and have a question about QFN voids

Hi folks! We have had the same success as Ben detailed. Our maximum void requirement is 50% of the pad and by using the window pane approach, we typically are getting 70%-80% coverage. We have had only two instances were we needed better coverage due to either a  component thermal or a grounding issue. We still used the window pane approach but had to conduct a series of DOEs to achieve the required coverage. 

And welcome back Ed!

Dave Hillman
Rockwell Collins
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"Gumpert, Ben" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
06/29/2012 12:15 PM
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Re: [TN] I'm back and have a question about QFN voids






Ed,

I'm interested to see what result you get with wave soldering, but I worry 
about e-mail access where you are going.

I've had good success with minimizing voids on QFNs by using a window-pane 
(array of apertures) on the center pad. I aim for 50% coverage of the 
center pad area. But you have to make sure that your signal pins can 
accommodate - either the solder paste reduction has to be the same for 
bottom only terminations, or you need a larger PCB pad (extending out from 
under the part) for excess solder to flow (so that the center pad solder 
determines the offset height of the part, not the perimeter solder 
joints.)

Ben

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ed Popeielarski
Sent: Friday, June 29, 2012 12:52 PM
To: [log in to unmask]
Subject: EXTERNAL: [TN] I'm back and have a question about QFN voids

Greetings 'netters,

For the past 2 1/2 years I've been lurking because Technet didn't get 
along with my employer's email system (specifically during maintenance).

I solved that problem by finding another employer! See how much you guys 
mean to me?!

It's good to be "back in the saddle again", so please allow me to begin 
with a perplexing question:

I need to solve QFN ground-pad voiding on a 0.038" thick ENIG assembly. 
The application is a high power RF amp and voiding as low as 25% causes 
issues with reliability.

Many attempts to resolve this with stencil variations, (thickness, star 
patterns, etc) and process variables (reflow time/temps) have been 
fruitless.

I'm considering re-spinning the board with a via dead center of this 6mm 
part, print & reflow only the leads, then wave solder the via (SAC305 with 
water soluble flux) in hopes of forcing the volatiles out from the center 
due to the wetting forces. Has anyone tried and succeeded with this method 
or am I sailing off the edge of the planet?

Thanks for your help in advance.


Ed Popielarski
Engineering Manager

Technical Services, Inc.
970 NE 21st Ct.
Oak Harbor, Wa. 98277

Ph: 360-675-1322
Fx: 206-624-0965
Cl: 949-581-6601

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