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June 2012

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Subject:
From:
"Upton, Shawn" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Upton, Shawn
Date:
Thu, 21 Jun 2012 20:20:28 +0000
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Yes, we had some issues with  rejects.  More of a pad issue, where the defect region (the outer 10%, IPC-6012 3.5.4.2.2, figure 3-5, pg 17, as opposed to the "pristine" 80% inner region) was way more than 10%, causing boards to be rejected.  While reading the specs, trying to understand better what is common practice for width, flatness, defect regions, etc; I came across this etch factor, figured that it was a similar thing that I should read into, and make sure I would not have issues with also.

Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336


-----Original Message-----
From: Smith, Rick [mailto:[log in to unmask]] 
Sent: Thursday, June 21, 2012 4:03 PM
To: 'TechNet E-Mail Forum'; Upton, Shawn
Subject: RE: Etch Factor

Hi Shawn,

Just curious what is the application? It seems that etch factor does not come up unless there is something very critical driving the concern.

Best Regards,
Rick

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Upton, Shawn
Sent: Wednesday, June 20, 2012 11:52 AM
To: [log in to unmask]
Subject: [TN] Etch Factor

Ok, got my specifications, looking at IPC-2221A Figure 10-3, for conductor width (see section 10.1.1 also, pages 77&79); and IPC-A-600H 3.2.1 (see page 86).  It looks like "etch factor" drives how much of a trapezoid one has on any given trace, although outer layers (since they are plated) may have overhang.

What I don't see is any qualitative numbers: ie, an etch factor of y +/-z is typical for outer layers, vs w for inner layers.  Are these numbers variable from vendor to vendor; and have to be called out on any given FAB drawing, since there isn't a generic number to be pointed at?

Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336


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