Paul,
I would against a call not allowing ANY voids in array device solder joints.
Frankly it is just not practical.
Bev
RIM

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Paul Reid
Sent: Wednesday, April 11, 2012 3:06 PM
To: [log in to unmask]
Subject: Re: [TN] Micro Stacked Via, solid copper plating, voiding

Hi Victor,

I do not know that this is covered by IPC documents or not but I know
that it can be a problem. 

Microvia voids have typically been acceptable if you do not violate the
minimum thickness requirement of the copper in the barrel of the hole. 

What we have is an enclosed void that has plating solution in the void
by default. The void cannot be plating closed without solution being
trapped in the void. This makes the void very susceptible to conductive
anodic filament (CAF) type of failure if there is a crack the goes to
the void. I spent years looking for that crack and finally found one.
Most voids do not produce a crack but on two occasions I have found
cracks into voided microvias. 

It is why I suggest that voids be avoided in any high end application.
It is not a standard but it is my take on this problem. Voids in plated
closed microvias should not be allowed is my suggestion to the 6012
committee.

I have sent pictures to Steve Gregory to post on his web site. You'll
note the plated closed microvias voids with cracks in the barrel on the
microvia. In two pictures you will see a blue crystal that is still in
the microvia that is from the plating solution. It is rare to find the
blue crystal because microsectioning flushes out the blue crystals
during processing.

Sincerely,  

 

Paul Reid 

Program Coordinator  

PWB Interconnect Solutions Inc. 
235 Stafford Rd., West, Unit 103 
Nepean, Ontario Canada, K2H 9C1 

613 596 4244 ext. 229  

Skype paul_reid_pwb 
[log in to unmask] 

 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
Sent: April 11, 2012 11:14 AM
To: [log in to unmask]
Subject: [TN] Micro Stacked Via, solid copper plating, voiding

Fellow TechNetters:

   I have searched for IPC documentation and/or Inductry Standards
concerning the acceptance/guidelines for solid plated micro via voidibg.
I did not locate any.  Can someone confirm that and/or provided guidance
as to which document covers that anomaly.

Victor,


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