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March 2012

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Subject:
From:
Phil Bavaro <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Mon, 26 Mar 2012 10:10:45 -0700
Content-Type:
text/plain
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text/plain (163 lines)
It is interesting that the crack also cracked through the legend ink.  I
suspect this happened after PWB fab.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Thayer, Wayne - IIW
Sent: Thursday, March 22, 2012 10:32 AM
To: [log in to unmask]
Subject: Re: [TN] EXTERNAL: [TN] Acceptability of Cracked Solder Mask

Be nice to figure out what caused the cracking, since that would give an
indication as to whether the underlying laminate is at risk.

But solder mask's job is to prevent solder wetting, and a cracked mask
can still do a fine job with that.  Matter of fact, I often don't even
put mask down in places which don't need it to block solder flow (like
across a dielectric which won't wet anyway).  Solder mask is not
intended as an electrical insulator (yes, I wear that t-shirt
regularly).

If the cracks mean that the soldermask is poorly cured or poorly
adhered, then it probably won't block solder well, so it may be no good.
But your pictures are of reflowed boards, so who really cares whether it
has mask covering dielectric or not?

Moisture ingress blocking has been brought up, but I doubt soldermasks,
which are typically loaded with completely acceptable pinholes AND have
generous clearances around pads, are much use there anyway.

Wayne Thayer

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
Sent: Thursday, March 22, 2012 12:04 PM
To: [log in to unmask]
Subject: Re: [TN] EXTERNAL: [TN] Acceptability of Cracked Solder Mask

You looking at pate 10-46 in revE?
Cracking of Solder mask:  A1, A2, D3.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Gumpert, Ben
Sent: Wednesday, March 21, 2012 3:39 PM
To: [log in to unmask]
Subject: Re: [TN] EXTERNAL: [TN] Acceptability of Cracked Solder Mask

Bill,

Looking again at your images, you could say that the cracks don't
actually bridge non-common circuits since you have non-solder mask
defined pads - the crack ends before it reaches another circuit.

Ben

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Gumpert, Ben
Sent: Wednesday, March 21, 2012 3:30 PM
To: [log in to unmask]
Subject: Re: [TN] EXTERNAL: [TN] Acceptability of Cracked Solder Mask

Bill,

I see the confusion; 610 mentions a target condition for cracks, but
then doesn't follow up with an acceptable or defect condition for
cracks.

But later in the document, a solder mask scratch that bridges non-common
circuits is indicated as a defect for all classes, so I would have to
say a crack bridging non-common circuits is also a defect for all
classes.

Ben

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of William Clark
Sent: Wednesday, March 21, 2012 3:03 PM
To: [log in to unmask]
Subject: EXTERNAL: [TN] Acceptability of Cracked Solder Mask

It is not clear to me from IPC 610-E if a crack in a solder mask
constitutes a Class 1 or Class 2 defect.  Pictures of the typical cracks
we are seeing are at the link below.  The crack in picture 3 repeats at
the same feature on every board in the array.  The cracks were not
visible on the bare board and the boards passed the tape test.  I'm
looking for input on the suitability of these boards.

Thanks

Bill

http://s1066.photobucket.com/albums/u408/clarkerg/



Bill Clark

Manufacturing Engineering and Quality Manager

ERG, <http://www.ergpower.com/>   Inc.  2601 Wayne Street, Endicott, NY
13760

607-754-9187





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